Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks

By Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo. Symposium on Field Programmable Gate Arrays, 2017

381 citations recorded by the source corpus.

Subfields: Computer Vision and Pattern Recognition, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/d99e059f3856269a28e718ba2390646544c0db71

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In Computer Vision and Pattern Recognition

In Electrical and Electronic Engineering

Citations in the corpus

Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs (2018, methodology): “[29] and [30] present their own optimization for ConvNets based on analytical performance models.”
Evaluating Fast Algorithms for Convolutional Neural Networks on FPGAs (2020, methodology): “Therefore, many previous works applied loop tiling strategy [3], [6], [13], [28], [37].”
Understanding Reuse, Performance, and Hardware Cost of DNN Dataflow: A Data-Centric Approach (2018, methodology): “First, we introduce a data-centric notation to represent various accelerator dataflows with data mappings and reuses being first-class entities, unlike the compute-centric notation used by prior proposals which infer the data reuses from a loop-nest representation [12, 25, 26, 30].”
FPGA-Based Accelerators of Deep Learning Networks for Learning and Classification: A Review (2019, methodology): “CONV Acceleration Architecture and Dataflow [83], where, Pix = Pox = 3, Piy = Poy = 3, and Pof = 3.”
A survey of FPGA-based accelerators for convolutional neural networks (2018, methodology): “To deal with this issue, tiling can be used which partitions the data fetched from memory into chunks (called tiles) that can fit in the cache [24].”
MAERI: Enabling Flexible Dataflow Mapping over DNN Accelerators via Reconfigurable Interconnects (2018, background): “[32] leverage loop blocking, unrolling, ordering to minimize storage in DRAM.”
Timeloop: A Systematic Approach to DNN Accelerator Evaluation (2019, background): “There is an abundance of excellent recent work on DNN accelerators [6], [13], [22], [26], [27], [32], [35]–[37].”
Automated systolic array architecture synthesis for high throughput CNN inference on FPGAs (2017, methodology): “In addition, The authors in [11] quantitatively analyze different optimization objects, and then propose a specific dataflow architecture to minimize data movements and memory accesses.”
AccPar: Tensor Partitioning for Heterogeneous Deep Learning Accelerators (2020, neutral): “…[36], OpenCL-FPGA-CNN [37] [126], Caffeine [38], DeepBurning [39], FPGA-DPCNN [40], TABLA [41], DNNWEAVER [42], FP-DNN [43], FPGA-LSTM [44], ESE [45], FPGA-Dataﬂow [46], FPGA-BNN [47], FPGA-Utilization [48], FFT-CNN [49], VIBNN [50], iSwitch [127], Shortcut-Mining [128], FA3C [129], E-RNN [130]”