Timeloop: A Systematic Approach to DNN Accelerator Evaluation

By Angshuman Parashar, Priyanka Raina, Yakun Sophia Shao, Yu-hsin Chen, Victor A. Ying, Anurag Mukkara, Rangharajan Venkatesan, Brucek Khailany, S. Keckler, Joel S. Emer. IEEE International Symposium on Performance Analysis of Systems and Software, 2019

671 citations recorded by the source corpus.

This paper presents Timeloop, an infrastructure for evaluating and exploring the architecture design space of deep neural network (DNN) accelerators. Timeloop uses a concise and unified representation of the key architecture and implementation attributes of DNN accelerators to describe a broad space of hardware topologies. It can then emulate those topologies to generate an accurate projection of performance and energy efficiency for a DNN workload through a mapper that finds the best way to schedule operations and stage data on the specified architecture. This enables fair comparisons across different architectures and makes DNN accelerator design more systematic. This paper describes Timeloop's underlying models and algorithms in detail and shows results from case studies enabled by Timeloop, which provide interesting insights into the current state of DNN architecture design. In particular, they reveal that dataflow and memory hierarchy co-design plays a critical role in optimizing energy efficiency. Also, there is currently still not a single architecture that achieves the best performance and energy efficiency across a diverse set of workloads due to flexibility and efficiency trade-offs. These results provide inspiration into possible directions for DNN accelerator research.

Subfields: Computer Vision and Pattern Recognition, Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/9ded246119861dd325e7004b2050bba310e08797

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Citations in the corpus

Understanding Reuse, Performance, and Hardware Cost of DNN Dataflow: A Data-Centric Approach (2018, methodology): “First, we introduce a data-centric notation to represent various accelerator dataflows with data mappings and reuses being first-class entities, unlike the compute-centric notation used by prior proposals which infer the data reuses from a loop-nest representation [12, 25, 26, 30].”
Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture (2019, methodology): “Mapping DNN layers to a tile-based architecture is a well-studied research problem [15, 25, 50].”
Domain-specific Genetic Algorithm for Multi-tenant DNNAccelerator Scheduling (2021, background): “Given a multitenant schedule, each sub-accelerator then schedules the job assigned to it via its own internal scheduler (which is the problem of mapping a DNN layer on a single PE array for which several solutions exist [11, 77]).”