Advanced high-K gate dielectric for high-performance short-channel In0.7Ga0.3As quantum well field effect transistors on silicon substrate for low power logic applications

By M. Radosavljevic, B. Chu-Kung, S. Corcoran, G. Dewey, M. Hudait, J. Fastenau, J. Kavalieros, W. K. Liu, D. Lubyshev, M. Metz and 5 more. International Electron Devices Meeting, 2009

161 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Materials Chemistry

View Paper: https://www.semanticscholar.org/paper/a8dd02a4131d2693cce80e4de8440f0a3c155b3d

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In Electrical and Electronic Engineering

1. K. Alam
2. Kelin J. Kuhn
3. Roger K. Lake
4. Bevan M. Baas
5. Aaron Stillmaker
6. Qiang Li
7. Kei May Lau

In Materials Chemistry

1. K. Alam
2. Kelin J. Kuhn
3. Roger K. Lake

Citations in the corpus

• Considerations for Ultimate CMOS Scaling (2012, methodology): “V devices have exploited many of these techniques, for example, in using InGaAs buried-channel structures equipped with an InP barrier layer using ALD TaSiOx as the dielectric [170].”
• Monolayer $\hbox{MoS}_{2}$ Transistors Beyond the Technology Road Map (2012, methodology): “These values measured by Intel [18] for their In0.”