Performance estimation of junctionless multigate transistors
By Chi-Woo Lee, Isabelle Ferain, A. Afzalian, Ran Yan, N. Akhavan, P. Razavi, Jean-Pierre Colinge. 2010
551 citations recorded by the source corpus.
Subfields: Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/a7a9bbe0778df02b888260417f24fe3c24d9657e
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In Electrical and Electronic Engineering
- Te-Kuang Chiang
- Kelin J. Kuhn
- Mansun Chan
- Isabelle Ferain
- Ran Yan
- Chi-Woo Lee
- Shengqi Yang
- Suresh Gundapaneni
Citations in the corpus
- Junctionless Multiple-Gate Transistors for Analog Applications (2011, background): “As demonstrated in [13] and [30], the performance of shortchannel JL devices is better than for IM transistors with the same mask channel length because the effective channel length of JL transistors is larger than the physical gate length, whereas in IM transistors, the effective channel length is ”
- A Junctionless Nanowire Transistor With a Dual-Material Gate (2012, background): “2192499 ied [1]–[3], and it has been demonstrated that junctionless”
- Comparison of Junctionless and Conventional Trigate Transistors With $L_{g}$ Down to 26 nm (2011, background): “Having the charge centroid near the center produces a higher equivalent electrical oxide thickness Tox and reduced gate control [2].”
- A Quasi-Two-Dimensional Threshold Voltage Model for Short-Channel Junctionless Double-Gate MOSFETs (2012, methodology): “It can be expected that the JLDM/JLAM device has the better immunity to SCEs than the JBIM device [16].”