Extreme scaling with ultra-thin Si channel MOSFETs

By Bruce B. Doris, M. Ieong, T. Kanarsky, Ying Zhang, R. Roy, O. Dokumaci, Zhibin Ren, F. Jamin, L. Shi, W. Natzle and 9 more. Digest. International Electron Devices Meeting,, 2002

190 citations recorded by the source corpus.

Subfields: Atomic and Molecular Physics, and Optics, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/93c5590e0c4ea8ef0740a56eff56e99300f36419

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In Electrical and Electronic Engineering

1. Onur Mutlu
2. Yu Cai
3. Erich F. Haratsch

Citations in the corpus

• Introduction to flash memory (2003, background): “I. INTRODUCTION The semiconductor market, for the long term, has been continuously increasing, even if with some valleys and peaks, and this growing trend is expected to continue in the coming years (see Fig.”
• The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance (2005, background): “The UTB SOI MOSFET [21]–[31] consists of a very thin ( tSi ≤ 10 nm), fully depleted (FD) transistor body to ensure good electrostatic control of the channel by the gate in the off state.”
• Innovative Materials, Devices, and CMOS Technologies for Low-Power Mobile Multimedia (2008, background): “Smallest transistors ever realized: (a) 8-nm STMicroelectronics [1], (b) 6-nm IBM [2], and (c) 4-nm NEC [3].”