Mnemosyne: lightweight persistent memory

By Haris Volos, A. J. Tack, Michael M. Swift. ASPLOS XVI, 2011

844 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Hardware and Architecture, Information Systems

View Paper: https://www.semanticscholar.org/paper/62957dc217fd2b416eb0ddb9b900eeff2e3fe169

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Computer Networks and Communications

In Hardware and Architecture

In Information Systems

Citations in the corpus

Evaluating STT-RAM as an energy-efficient main memory alternative (2013, methodology): “Phase change memory (PCRAM) has been proposed as a promising alternative to commodity DRAM [10], [12], [59], and there has been significant effort in making optimizations to PCRAM-based main memory to improve its latency, energy, and endurance.”
Persistent B+-Trees in Non-Volatile Main Memory (2015, methodology): “There are wide-spread discussions on incorporating NVM technologies to substitute or complement DRAM as the main memory in future computer systems [5, 9, 36, 15, 26, 7, 31, 8, 33, 29, 20].”
An Empirical Guide to the Behavior and Use of Scalable Persistent Memory (2019, methodology): “Common ways to emulate NVM include adding delays to memory accesses in software [32,36,49], using software emulators [43,47], using software simulation [12,31,40], using hardware emulators such as Intel’s Persistent Memory Emulator Platform (PMEP) [21] to limit latency and bandwidth [54, 55, 60], us”
Basic Performance Measurements of the Intel Optane DC Persistent Memory Module (2019, background): “Over the past decade, they have written a slew of papers proposing new programming models [4, 31], file systems [33, 34, 32, 30, 5, 13], libraries [2, 3, 25], and applications built to exploit the performance and flexibility that NVDIMMs promised to deliver.”
Approximate storage in solid-state memories (2013, background): “more recently, flat address spaces [10, 45].”
FPTree: A Hybrid SCM-DRAM Persistent and Concurrent B-Tree for Storage Class Memory (2016, neutral): “Several works proposed global solutions to these challenges, such as NVHeap [10], Mnemosyne [26], and REWIND [7], which are based on garbage collection and software transactional memory.”
A simpler, safer programming and execution model for intermittent systems (2015, background): “Mnemo-syne [37] is an interface to persistent storage and heap data.”
Alpaca: intermittent execution without checkpoints (2017, background): “…in non-volatile memory, and for building consistent memory and file systems out of byte-addressable non-volatile memory [Coburn et al. 2011; Condit et al. 2009; Doshi and Varman 2012; Dulloor et al. 2014; Moraru et al. 2013; Narayanan and Hodson 2012; Venkataraman et al. 2011; Volos et al. 2011].”
In-Memory Big Data Management and Processing: A Survey (2015, background): “General libraries and programming interfaces are proposed to expose NVRAM as a persistent heap, enabling NVRAM adoption in an easy-to-use manner, such as NV-heaps [214], Mnemosyne [215], NVMalloc [216], and recovery and durable structures [213], [217].”
Memory persistency (2014, background): “Recent work has suggested alternative interfaces to enforce NVRAM write order and guarantee proper recovery, for example, durable transactions and persist barriers [28, 10].”
Efficient virtual memory for big memory servers (2013, background): “– Charles Thacker, 2010 ACM Turing Award Lecture.”
NOVA: A Log-structured File System for Hybrid Volatile/Non-volatile Main Memories (2016, methodology): “Researchers have proposed several approaches to integrating NVMs into computer systems [11] [13] [19] [31] [36] [41] [58] [67], and the most exciting proposals place NVMs on the processor's memory bus alongside conventional DRAM, leading to hybrid volatile/non-volatile main memory systems [4] [51]…”
NV-Tree: Reducing Consistency Cost for NVM-based Single Level Systems (2015, background): “However, the atomicity of memory writes can only be supported with a very small granularity or no more than the memory bus width (8 bytes for 64-bit CPUs) [25] which is addressed in previous work [55, 14, 44], so updating”
Trends in big data analytics (2014, neutral): “memory transactions [97, 47].”
UNITY: Unified Memory and File Space (2017, methodology): “Mnemosyne [35] provides compiler support and primitives for automatic persistence of application data to NVRAM.”