Cache-Collision Timing Attacks Against AES

By Joseph Bonneau, Ilya Mironov. Workshop on Cryptographic Hardware and Embedded Systems, 2006

409 citations recorded by the source corpus.

Subfields: Artificial Intelligence, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/903ba3226b51382679810b1b727481c132c1ce94

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Citations in the corpus

SIMON and SPECK: Block Ciphers for the Internet of Things (2015, background): “, AES, on processors with cache memory can be particularly vulnerable to these cache-timing attacks [18].”
Yet another MicroArchitectural Attack:: exploiting I-Cache (2007, neutral): “[31, 39, 40, 7, 8, 29, 30, 11, 25, 22, 24, 32, 12, 13].”
Wait a Minute! A fast, Cross-VM Attack on AES (2014, background): “Bonneau and Mironov’s study [9] shows how to exploit cache collisions in AES as a source for time leakage.”
Efficient Cache Attacks on AES, and Countermeasures (2010, methodology): “This was improved by Bonneau and Mironov [15] (attacking the first or last round) and by Acıiçmez et al.”
A Formal Foundation for Secure Remote Execution of Enclaves (2017, background): “Side channel observations, such as attacks observing cache timing, are known to compromise cryptographic keys used by numerous cryptosystems [10, 13, 14, 34].”
The Skein Hash Function Family (2009, methodology): “For example, AES has been successfully cryptanalyzed using a side channel associated with its table lookups [12, 20].”
A survey of microarchitectural timing attacks and countermeasures on contemporary hardware (2016, background): “Bonneau and Mironov [30] and Aciiçmez et al. [10] both further explored these self-contention channels in AES in OpenSSL (versions 0.9.8a and 0.9.7e).”
Intel SGX Explained (2016, methodology): “Despite these difficulties, cache timing attacks are known to retrieve cryptographic keys used by AES [25, 146], RSA [28], Diffie-Hellman [123], and elliptic-curve cryptography [27].”
HomeAlone: Co-residency Detection in the Cloud via Side-Channel Analysis (2011, neutral): “, [43], [42], [35], [8], [5], [15], [33], [34], [44], [23], [40], [25], [30], [16], [37], [49], [14], [24],”
DAWG: A Defense Against Cache Timing Attacks in Speculative Execution Processors (2018, positive): “1) Cache tag state based attacks: Attacks using cache tag state-based channels are known to retrieve cryptographic keys from a growing body of cryptographic implementations: AES [7], [40], RSA [9], Diffie-Hellman [32], and ellipticcurve cryptography [8], to name a few.”
Faster and Timing-Attack Resistant AES-GCM (2009, background): “[18], Bonneau and Mironov [9], and Neve et al.”
Controlled-Channel Attacks: Deterministic Side Channels for Untrusted Operating Systems (2015, background): “Cache side-channel attacks [47], [12], [40], [7], [8], [14], [46], [44], [52] are most closely related to the attacks described in this paper, as both exploit”
CacheZoom: How SGX Amplifies The Power of Cache Attacks (2017, background): “he timing attacks are based on the fact that a spy process can measure the differences in memory access times. These attacks are proposed to recover cryptography keys of ciphers such as DES [51], AES [11] and RSA [43]. Although there exist solutions to make cryptographic implementation resistant to ”