Three-dimensional integrated circuits for low-power, high-bandwidth systems on a chip
By J. Burns, L. McIlrath, C. Keast, C. Lewis, A. Loomis, K. Warner, P. Wyatt. 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177), 2001
167 citations recorded by the source corpus.
Subfields: Automotive Engineering, Electrical and Electronic Engineering, Mechanical Engineering
View Paper: https://www.semanticscholar.org/paper/8c5d8fe2e348ab4772fc660a0df685add51cb1ef
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In Electrical and Electronic Engineering
- Ralph Etienne-Cummings
- Eugenio Culurciello
- Jian-Qiang Lu
- B. Linares‐Barranco
- T. Serrano‐Gotarredona
- Shih-Chii Liu
- Giacomo Indiveri
- Tobi Delbruck
In Mechanical Engineering
Citations in the corpus
- Megapixel CMOS image sensor fabricated in three-dimensional integrated circuit technology (2005, background): “8μm gate length SOI-CMOS, epoxy adhesive bonding, and 6μm diameter 3D-vias [2].”
- 3-D Hyperintegration and Packaging Technologies for Micro-Nano Systems (2009, background): “Vol. 97, No. 1, January 2009 | Proceedings of the IEEE 21 materials, such as nonoutgassing adhesives [21], [ 25 ], [32], [43], [45], [47]–[49], plasma-enhanced chemical vapor deposition (PECVD) oxide [24], [26], and few metals (e.g., copper [23], [27]–[31], titanium [50], [51], InAu [33], and CuSn [”
- A biomorphic digital image sensor (2003, background): “D) integration techniques promise small footprints with pixel-parallel spatiotemporal image processing [3], [4].”
- 8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology (2009, unknown): “Digital Object Identifier 10.1109/JSSC.2009.2034408 [5], [6].”