Hybrid memory cube new DRAM architecture increases density and performance

By Joe M. Jeddeloh, B. Keeth. Symposium on VLSI Technology, 2012

445 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/8b04ea524cb6ced72868c120a00c4679d84be006

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Computer Networks and Communications

In Electrical and Electronic Engineering

In Hardware and Architecture

Citations in the corpus

A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets (2018, background): “ertically connected vaults, with individual memory controllers on the LoB. Trafﬁc between the serial links and vaults is transported by the means of an all-to-all network (logically a crossbar) [24], [25], [26], [27], [28]. Our architecture consists of multiple processing clusters attached to a cros”
Neurocube: A Programmable Digital Neuromorphic Architecture with High-Density 3D Memory (2016, methodology): “The logic and memory dies can be fabricated in different process technologies; e.g., DRAM dies are fabricated in 50nm and logic die is fabricated in 28nm [20].”
Efficient Processing of Deep Neural Networks: A Tutorial and Survey (2017, methodology): “le of using eDRAM for DNN processing can be found in DaDianNao [89], which uses 36MB of eDRAM to store the weights for the fully-connected layers. 3-D memory, such as Micron’s Hyper Memory Cube (HMC) [94], stacks the DRAM on top of the logic using through silicon vias (TSV); this results in an order”
PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory (2016, unknown): “This architecture design is compatible with the hybrid memory cube (HMC) [57] and high bandwidth memory (HBM) [58].”
GraphPIM: Enabling Instruction-Level PIM Offloading in Graph Computing Frameworks (2017, methodology): “5 [33] and compute the energy of HMC SerDes links, DRAM layers, and functional units using the energy models from prior works [34]–[36].”
A scalable processing-in-memory accelerator for parallel graph processing (2015, methodology): “For example, checking the condition ‘diff > e’ in line 19 of Figure 1 can be done using this mechanism.”
Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks (2018, methodology): “4mm 2 per vault to implement our PIM logic [30, 36, 74].”
Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology (2017, unknown): “, Hybrid Memory Cube [6, 51]).”
TETRIS: Scalable and Efficient Neural Network Acceleration with 3D Memory (2017, methodology): “The HMC stack (Figure 2 left) is vertically divided into sixteen 32-bit-wide vaults [21], which are similar to conventional DDRx channels and can be accessed independently.”
CACTI 7 (2017, methodology): “The graph shows memory power dissipation as the hit rate in the HMC cache is varied.”