Register organization for media processing

By Scott Rixner, William (Bill) J. Dally, Brucek Khailany, Peter R. Mattson, U. Kapasi, John Douglas Owens. Proceedings Sixth International Symposium on High-Performance Computer Architecture. HPCA-6 (Cat. No.PR00550), 2000

307 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/8a29b6e1bdef9ccdce0fd5580bae44bceb95814e

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Electrical and Electronic Engineering

1. S. Keckler
2. Doug Burger
3. William (Bill) J. Dally
4. Mark A. Horowitz
5. Nuwan Jayasena
6. Derek M. Jones
7. Onur Mutlu
8. Giovanni De Micheli

In Hardware and Architecture

1. S. Keckler
2. Mark A. Horowitz
3. Doug Burger
4. Nuwan Jayasena
5. William (Bill) J. Dally
6. Onur Mutlu
7. Derek M. Jones
8. Thomas Moscibroda

Citations in the corpus

• Smart Memories: a modular reconfigurable architecture (2000, background): “The LRF structure provides the necessary bandwidth more efficiently in terms of area, power, and access time compared to increasing the number of ports to the shared register file [25, 32 ].”
• Multiple-banked register file architectures (2000, background): “Several partitioned register file organizations for media processing were proposed in [9].”
• Clock rate versus IPC: the end of the road for conventional microarchitectures (2000, methodology): “Consequently, the bypass logic complexity and bypass data transmission delay will be substantial barriers to improved performance [18, 20].”