Interconnect limits on gigascale integration (GSI) in the 21st century

By Jeff Davis, R. Venkatesan, Alan Kaloyeros, Michael Beylansky, Shukri J. Souri, Kaustav Banerjee, Krishna C. Saraswat, Arifur Rahman, R. Reif, James D. Meindl. Proceedings of the IEEE, 2001

536 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/7a02c74df3ad849d1477395655f6af26ee10baa4

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In Electrical and Electronic Engineering

1. Igor L. Markov
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4. Robert W. Keyes
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Citations in the corpus

• Magnonic logic circuits (2010, background): “Besides that, the growing number of devices per unit area results in tremendous difficulties with interconnection wiring [2].”
• Physical limits of silicon transistors and circuits (2005, background): “They are successful in being able to fit the length distributions of manufactured working chips (Donath 1979, 1981, Davis et al 1996, 1998a, 2001).”
• Limits on fundamental limits to computation (2014, methodology): “As suggested in [17,18], it can be enriched by analysis of limits.”
• Three-dimensional integrated circuits (2006, background): “Initial analyses of investigated 3D wire-length reduction [11] showed that 3D integration indeed provides a smaller”