Comprehensive study of the resistivity of copper wires with lateral dimensions of 100 nm and smaller

By W. Steinhögl, G. Schindler, G. Steinlesberger, M. Traving, M. Engelhardt. 2005

526 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Electronic, Optical and Magnetic Materials

View Paper: https://www.semanticscholar.org/paper/66ece36d01c94c5fc0e5fadbd0b3dac9182cf872

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In Electrical and Electronic Engineering

In Electronic, Optical and Magnetic Materials

Citations in the corpus

Energy dissipation and transport in nanoscale devices (2010, background): “For instance, the electrical resistivity of Cu interconnects with line widths below 100 nm increases by more than a factor of two from the bulk Cu resistivity [130], and the resistivity for line widths near 40 nm was shown to increase by at least a factor of four [131, 132] at room temperature.”
Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status, and Prospects (2009, background): “specularity value [50]), the delay of doped GNR interconnect could be as much as 40% worse than that of Cu.”
Conductance Modeling for Graphene Nanoribbon (GNR) Interconnects (2007, background): “3 as average values of the reported measured data [11], [12].”
Crosstalk Prediction of Single- and Double-Walled Carbon-Nanotube (SWCNT/DWCNT) Bundle Interconnects (2009, background): “At the submicrometer region, copper (Cu) interconnects, which are being employed at present technology nodes, will encounter some serious limitations, such as scattering by electron surface and grain boundary [1].”
Fundamental transmitting properties of carbon nanotube antennas (2005, background): “In particular, for 50 50 nm copper traces, the resistivity was approximately twice as large as the bulk value for copper [25].”
On the Applicability of Single-Walled Carbon Nanotubes as VLSI Interconnects (2009, background): “The widening gap between ITRS current-density requirements [14] and the current-carrying capacity of Cu vias—primarily due to the steep rise in parasitic resistance of aggressively scaled Cu interconnects [14]–[16] and rising on-chip metal temperatures—is shown in Fig.”
Scaling analysis of multilevel interconnect temperatures for high-performance ICs (2005, background): “I. INTRODUCTION ACCURATE estimates of multilevel interconnect temper-atures are necessary for interconnect performance and reliability assessment in high-performance very large-scale integrated (VLSI) circuits [1]–[3].”