Scaling trends of cosmic ray induced soft errors in static latches beyond 0.18 /spl mu/
By T. Karnik, B. Bloechel, K. Soumyanath, Vivek De, S. Borkar. 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185), 2001
139 citations recorded by the source corpus.
Subfields: Nuclear and High Energy Physics, Radiation
View Paper: https://www.semanticscholar.org/paper/64ec2ac82d95e0dcc017a3003e0b2830efb230f5
How researchers see this paper
The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.
- Joel S. Emer
- Christopher T. Weaver
- Shubhendu S. Mukherjee
- Steven K. Reinhardt
- T. Karnik
- J. Patel
- P. Hazucha
- Todd M. Austin
Citations in the corpus
- A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor (2003, background): “Current predictions show that typical raw FIT rate numbers for latches and SRAM cells vary between 0.001 – 0.01 FIT/bit at sea level ([24],[17],[ 12 ],[11]).”
- Techniques to reduce the soft error rate of a high-performance microprocessor (2004, background): “The raw error rate per latch or SRAM bit is projected to remain roughly constant or decrease slightly for the next several technology generations [9][ 11 ].”
- The soft error problem: an architectural perspective (2005, background): “The raw error rate per device (e.g., latch, SRAM cell) in a bulk CMOS process is projected to remain roughly constant or decrease slightly for the next several technology generations [6][ 7 ].”
- Characterization of soft errors caused by single event upsets in CMOS processes (2004, background): “Careful selection of a test circuit is important in order to decouple the effects of critical charge, transistor type, and diode area, and also to cover a sufficient range of values of these parameters [71], [72].”