Hybrid memory cube (HMC)

By J. T. Pawlowski. IEEE Hot Chips Symposium, 2011

431 citations recorded by the source corpus.

View Paper: https://www.semanticscholar.org/paper/54a15f2c25bec4274d5bb423dbc5002426a506a3

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Hardware and Architecture

Citations in the corpus

NDA: Near-DRAM acceleration architecture leveraging commodity DRAM devices and standard memory modules (2015, background): “[71] J. T. Pawlowski, “Hybrid memory cube (HMC),” in Hot Chips 23, 2011.”
Pinatubo: A processing-in-memory architecture for bulk bitwise operations in emerging non-volatile memories (2016, background): “For example, the internal bandwidth in the hybrid memory cube (HMC) [20] is 128 times larger than its SerDes interface [4].”
In-memory computing with resistive switching devices (2018, background): “Another solution is the introduction of memory chips with enhanced bandwidth, such as the hybrid memory cube (HMC) 7 , and high bandwidth memory (HBM) 8 , where high data-transfer rate and high memory density are achieved by stacking multiple memory chips by through-silicon via (TSV) interconnects.”
GraphPIM: Enabling Instruction-Level PIM Offloading in Graph Computing Frameworks (2017, background): “Several PIM architectures and programming models have been recently proposed by academia [12]–[14], and memory vendors have also started to incorporate compute units into the memory architecture, such as Hybrid Memory Cube (HMC) proposed by Micron [15].”
Memory devices and applications for in-memory computing (2020, background): “This concept known as near-memory computing has benefitted significantly from recent advances in die stacking technology 7 and the commercialization of advanced memory modules such as the hybrid memory cube (HMC) 8 and high bandwidth memory (HBM) 9 .”
DRISA: A DRAM-based Reconfigurable In-Situ Accelerator (2017, background): “• Processing-in-Memory Architectures: On one hand, there is plenty of recent work on PIM [10, 12, 16, 18, 20, 30, 32, 34, 36, 42, 46, 52, 53, 67, 73, 73, 75, 76, 88, 93, 95] that built lightweight processors, reconfigurable or application-specific logics in the logic die of HMC [74] or HBM [58].”
A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets (2018, background): “Given the manufacturer and [10], the device seems to be a reasonable reference for early HMCs.”
CACTI 7 (2017, background): “…power numbers for the various components are derived from a survey [Lee et al. 2009a; Poulton et al. 2009; OMahony et al. 2010; Palmer et al. 2008; Pawlowski 2011; Intel 2014] and divided into three types based on the length of the interconnect: short ( < 2inches), mid ( < 10inches), and long ( >…”
TOP-PIM: throughput-oriented programmable processing in memory (2014, methodology): “We loosely model the memory interfaces from host to memory stacks on publicly available data on HMC [3, 37].”