Effective Capacitance and Drive Current for Tunnel FET (TFET) CV/I Estimation

By S. Mookerjea, R. Krishnan, Suman Datta, Vijay Narayanan. IEEE Transactions on Electron Devices, 2009

200 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/44f68f0bb033b5285152cb8c44ada2c525168a8c

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In Electrical and Electronic Engineering

1. Luca Selmi
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4. Steven J. Koester
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Citations in the corpus

• Inverters With Strained Si Nanowire Complementary Tunnel Field-Effect Transistors (2013, background): “Clear voltage overshoot is observed because of the large Miller capacitance of the TFET structure [20], [21].”
• Low-Voltage Tunnel Transistors for Beyond CMOS Logic (2010, unknown): “Currently, there are projections based on circuit models generated from a variety of TFET simulations [53], [93]–[95] as seen in Fig.”
• On the Possibility of Obtaining MOSFET-Like Performance and Sub-60-mV/dec Swing in 1-D Broken-Gap Tunnel Transistors (2010, methodology): “Even though additional refinement for the delay estimate can be obtained by using an “effective drive current” model [35], the above relation is sufficient for”