On Monolayer ${\rm MoS}_{2}$ Field-Effect Transistors at the Scaling Limit

By Leitao Liu, Yang Lu, Jing Guo. IEEE Transactions on Electron Devices, 2013

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A roadmap for electronic grade 2D materials (2019, background): “[19]) which lie on the lowest energy-delay product”
Progress in Contact, Doping and Mobility Engineering of MoS2: An Atomically Thin 2D Semiconductor (2018, background): “, with results showing that MoS2 FETs can have a 52% smaller drain-induced barrier lowering (DIBL) and a 13% smaller subthreshold swing (SS) than 3-nm-thick-body Si FETs at an LCH of 10 nm with the same gating [123].”
MoS2 transistors with 1-nanometer gate lengths (2016, background): “For example, monolayer and few-layer MoS2 have been shown theoretically to be superior to Si at the sub-5-nm scaling limit (17, 18).”
Electronics based on two-dimensional materials. (2014, background): “For example, Liu et al.(81) have shown that MoS2 FETs can comply with the ITRS down to a minimum channel length of 8 nm, whereas silicon MOSFETs can go down to a channel length of 10 nm with UTB of 3 nm.”
Benchmarking of Beyond-CMOS Exploratory Devices for Logic Integrated Circuits (2015, methodology): “Several devices currently under study at NRI and STARnet centers have been added: ITFET [13] aka SymFET [14], FEFET [15], NCFET [16], PiezoFET [17], MITFET [18], CSL [19], ExFET [5], ThinTFET [20], GaNTFET [21], TMDTFET [22], and van der Wall FET (vdwFET) [23].”