Metal-Ferroelectric-Meta-Oxide-semiconductor field effect transistor with sub-60mV/decade subthreshold swing and internal voltage amplification
By A. Rusu, Giovanni A. Salvatore, David Jiménez, Adrian M. Ionescu. International Electron Devices Meeting, 2010
219 citations recorded by the source corpus.
This work reports the first complete experimental demonstration and investigation of subthreshold swing, SS, smaller than 60 mV/decade, at room temperature, due to internal voltage amplification in FETs with a Metal-Ferroelectric-Metal-Oxide gate stack. The investigated p-type MOS transistor is a dedicated test structure to explore the negative capacitance effect by probing the internal voltage between the P(VDF-TrFE) and SiO2 dielectric layers of the gate stack. We find that the region of internal surface potential amplification, dψS/dVg>1, corresponds to an S-shape of the polarization versus ferroelectric voltage (associated with negative capacitance). In Fe-FETs the internal voltage amplification could significantly lower their SS, even without reaching sub-60mV/dec values. SSmin as low as 46 to 58 mV/decade and average swings, SSavg, as small as 51 to 59 mV/dec are observed for the first time in a minor loop hysteretic characteristics of Fe-FETs.
Subfields: Electrical and Electronic Engineering, Materials Chemistry
View Paper: https://www.semanticscholar.org/paper/1c991070e21b4fa89f22f58ac41bd7347582b6f1
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Citations in the corpus
- Effects of the Variation of Ferroelectric Properties on Negative Capacitance FET Characteristics (2016, background): “bilayers [4], [5]; and 3) superlattices [6] and ferroelectricgated transistors [7]–[9].”
- Steep Slope and Near Non-Hysteresis of FETs With Antiferroelectric-Like HfZrO for Low-Power Electronics (2015, background): “The polymer FE was studied and integrated for a <60mV/decade swing [3], [4] for low-power operation applications.”