CMOS Photonics for High-Speed Interconnects

By C. Gunn. IEEE Micro, 2006

505 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/1118a4aa1a2c65516ad1cc30fdf2c2541cce8999

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In Electrical and Electronic Engineering

Citations in the corpus

On the Design of a Photonic Network-on-Chip (2007, methodology): “The integration of modulators, waveguides and photodetectors with CMOS integrated circuits for off-chip communication has been reported and recently became commercially available [8].”
Silicon Photonics (2006, methodology): “A more comprehensive review can be found in [63].”
Low-Threshold Heterogeneously Integrated InP/SOI Lasers With a Double Adiabatic Taper Coupler (2012, background): “S ILICON photonics is drawing increasing attention due to the promise of fabricating low-cost, compact circuits that integrate photonic and microelectronic elements [1].”
Hybrid Silicon Photonics for Optical Interconnects (2011, background): “This chip can be a (single or array) vertical-cavity surface-emitting laser-type laser flip-chip bonded to the silicon chip [18].”
Progress in Low-Power Switched Optical Interconnects (2011, methodology): “We note that while this paper has thus far assumed a CMOS photonics platform built in an SOI process [35], the discussion on circuit power scaling presented below is generally true for a variety of proposed silicon photon-”
50-Gb/s Silicon Optical Modulator (2012, background): “Many demonstrations of modulation at around 10Gb/s have been reported from such structures [5-16] and a few at 40Gb/s [17-19].”
Roadmapping the next generation of silicon photonics (2023, background): “This scaling is enabled by an exponential increase over time in the economic scale of the semiconductor industry, which allows the industry to pay for ever more expensive foundries and process development.”
Compact Single-Mode Silicon Hybrid Rib/Strip Waveguide With Adiabatic Bends (2011, background): “The main advantage of using silicon for photonics is that it is possible to use the existing complementary metal–oxide semiconductor (CMOS) manufacturing infrastructure [ 1 ], [2], while at the same time having a material system that is both transparent at telecom wavelengths and provides a high ind”
Hybrid III--V on Silicon Lasers for Photonic Integrated Circuits on Silicon (2014, background): “INTRODUCTION Silicon photonics is attracting a lot of attention due to the prospect of low-cost, compact circuits t hat integrate photonic and microelectronic elements on a single chip [1,2] .”
A Grating-Coupler-Enabled CMOS Photonics Platform (2011, background): “form [1]–[3] that allows monolithic integration of the photonic circuit with electronic driver, control, and receiver circuitry.”
Silicon-photonic clos networks for global on-chip communication (2009, background): “Restrictions apply. thick layer of buried oxide (BOX) [5], or in a separate layer of silicon nitride (SiN) deposited on top of the metal stack [2].”
Review of Silicon Photonics Foundry Efforts (2014, unknown): “130-nm CMOS silicon-on-insulator (SOI) technology node [12], [13].”