Layout techniques to enhance the radiation tolerance of standard CMOS technologies demonstrated on a pixel detector readout chip
By W. Snoeys, F. Faccio, M. Burns, M. Campbell, E. Cantatore, N. Carrer, L. Casagrande, A. Cavagnoli, C. Dachs, S. Liberto and 23 more. 2000
170 citations recorded by the source corpus.
Subfields: Electrical and Electronic Engineering, Nuclear and High Energy Physics, Radiation
View Paper: https://www.semanticscholar.org/paper/10847f21cff9965589855f7184c9d21908746c14
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In Electrical and Electronic Engineering
In Nuclear and High Energy Physics
Citations in the corpus
- Radiation-induced edge effects in deep submicron CMOS transistors (2005, background): “The results presented were obtained on laboratory-grade oxides, but were verified on commercial-grade oxides around a decade later, when available commercial CMOS processes with lithographic dimensions as small as 250 nm were using gate oxides 5.2 nm thick [ 3 ].”
- Design and performance of the CMS pixel detector readout chip (2005, methodology): “The design has been made radiation tolerant by following special layout rules as proposed in [5].”