Design and performance of the CMS pixel detector readout chip

By H. Kaestli, M. Barbero, W. Erdmann, C. Hoermann, R. Horisberger, D. Kotlinski, Beat H. Meier. 2005

138 citations recorded by the source corpus.

The readout chip for the CMS pixel detector has to deal with an enormous data rate. On-chip zero suppression is inevitable and hit data must be buffered locally during the latency of the first level trigger. Dead-time must be kept at a minimum. It is dominated by contributions coming from the readout. To keep it low an analog readout scheme has been adopted where pixel addresses are analog coded. We present the architecture of the final CMS pixel detector readout chip with special emphasis on the analog readout chain. Measurements of its performance are discussed.

Subfields: Electrical and Electronic Engineering, Nuclear and High Energy Physics

View Paper: https://www.semanticscholar.org/paper/952260c5271d9f9c89a66274e68179b3a069c570

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Citations in the corpus

The CMS experiment at the CERN LHC (2008, background): “25μm 5-metal-layer CMOS process and contains 52 ×80 pixels [25].”
Description and performance of track and primary-vertex reconstruction with the CMS tracker (2014, methodology): “In the data acquisition system of the pixel detector [14], zero-suppression is performed in the readout chips of the sensors [15], with adjustable thresholds for each pixel.”
Description and performance of track and primary-vertex reconstruction with the CMS tracker: JINST 9 (2014) 10, P10009 (2014, methodology): “In the data acquisition system of the pixel detector [14], zero-suppression is performed in the readout chips of the sensors [15], with adjustable thresholds for each pixel.”