Understanding sources of ineffciency in general-purpose chips

By Rehan Hameed, Wajahat Qadeer, Megan Wachs, Omid Azizi, A. Solomatnikov, Benjamin C. Lee, Stephen Richardson, Christos Kozyrakis, Mark A. Horowitz. 2011

251 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Hardware and Architecture, ML Systems & Hardware

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Citations in the corpus

Chasing Carbon: The Elusive Environmental Footprint of Computing (2020, background): “For salient applications, such as AI [4]–[9], molecular dynamics [10], video encoding [11], and cryptography [12], systems now comprise specialized hardware accelerators that provide orders-of-magnitude higher performance and energy efﬁciency.”
Cambricon-X: An accelerator for sparse neural networks (2016, background): “Due to stringent energy constraints, hardware accelerators have emerged as an energy efficient alternative of CPUs and GPUs [1]–[6].”
Neural Acceleration for General-Purpose Approximate Programs (2012, background): “Recent work has quantiﬁed three orders of magnitude of difference in efﬁciency between general-purpose processors and ASICs [21,36].”
Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks (2016, background): “Since data movement can be more energy-consuming than computation [10], [11], the processing of CNNs has to not only provide high parallelism for high throughput but also optimize for the data movement of the entire system in order to achieve high energy efﬁciency.”
Convolution engine: balancing efficiency & flexibility in specialized computing (2013, methodology): “However, SIMD units are still one to two orders of magnitude less efficient compared to algorithm-specific custom units [20].”
DianNao: a small-footprint high-throughput accelerator for ubiquitous machine-learning (2014, methodology): “Our study not only confirms previous observations that dedicated storage is key for achieving good performance and power [14], but it also highlights that, beyond exploiting locality at the level of registers located close to computational operators [33, 38], considering memory as a prime-order conc”
FPGA-Based Accelerators of Deep Learning Networks for Learning and Classification: A Review (2019, background): “The authors in [72], [73] proved that the highest energy expense results from accessing the off-chip DRAM memory for data movement rather than computation.”
Limits on fundamental limits to computation (2014, background): “They speed up biomolecular simulation 100-fold [5, 6] and improve the efficiency of video decoding 500-fold [7], but require design effort with keen understanding of specific computations, impose high costs and financial risks, need markets where general-purpose computers lag behind, and often canno”
DaDianNao: A Machine-Learning Supercomputer (2014, background): “Our community is well aware of the trend towards heterogeneous computing where architecture specialization is seen as a promising path to achieve high performance at low energy [21], provided we can ﬁnd ways to reconcile architecture specialization and ﬂexibility.”
Planaria: Dynamic Architecture Fission for Spatial Multi-Tenant Acceleration of Deep Neural Networks (2020, background): “As such, accelerators are put in the spotlight to enable performance improvements necessary for emerging workloads [10].”
There’s plenty of room at the Top: What will drive computer performance after Moore’s law? (2020, background): “Hardware that is customized for an application domain can bemuchmore streamlined and use many fewer transistors, enabling applications to run tens to hundreds of times faster (46).”
Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks (2016, background): “Although these operations can leverage highly-parallel compute paradigms, such as SIMD/SIMT, throughput may not scale accordingly due to the accompanying bandwidth requirement, and the energy consumption remains high as data movement can be more expensive than computation [11] [12] [13].”