Cambricon-X: An accelerator for sparse neural networks

By Shijin Zhang, Zidong Du, Lei Zhang, Huiying Lan, Shaoli Liu, Ling Li, Qi Guo, Tianshi Chen, Yunji Chen. 2016

719 citations recorded by the source corpus.

Subfields: Computer Vision and Pattern Recognition, Electrical and Electronic Engineering, Efficiency & Compression

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Citations in the corpus

Chasing Carbon: The Elusive Environmental Footprint of Computing (2020, background): “rk includes system-performance increases, power management and energy-efﬁciency optimization through dynamic voltage and frequency scaling (DVFS) [96], [97], [101]–[111], and specialized hardware [4]–[9]. As Figure9and Figure10 show, architectural improvements have considerably reduced the operation”
To prune, or not to prune: exploring the efficacy of pruning for model compression (2017, background): “y has sparse connection matrices, so efﬁcient inference using these sparse models requires purpose-built hardware capable of loading sparse matrices and/or performing sparse matrix-vector operations (Zhang et al., 2016; Han et al., 2016; Parashar et al., 2017). Also, representing sparse matrices car”
Demystifying Parallel and Distributed Deep Learning (2018, background): “, after compression) is a focus for some ASICs [269], and advances in recurrent networks and attention learning [30,253] indicate that training and inference hardware would also need to work efficiently with variable-length inputs.”
Recent Advances in Convolutional Neural Network Acceleration (2018, background): “Cambricon-X [134] ASIC 56KB on-chip SRAM 1 GHz 544 GOPS”
AccPar: Tensor Partitioning for Heterogeneous Deep Learning Accelerators (2020, neutral): “[17], TrueNorth [18–20], MT-spike [21], PT-spike [22] DNN Co-processor NPU [23], DianNao-family [24–27], Cambricon [28], Cambricon-x [29], TPU [30,31], ScaleDeep [32], Stripes [33], Neural Cache [123,124], Diffy [125] FPGA FPGA-DCNN [34], Embedded-FPGA-CNN [35], FPGA-Exploration [36],…”
Enhancing Quality for HEVC Compressed Videos (2017, neutral): “energy [41].”
AWB-GCN: A Graph Convolutional Network Accelerator with Runtime Workload Rebalancing (2019, background): “Zhang et al. [39] propose Cambricon-S with efﬁcient index matching to identify and multiplex non-zeros and feed them to massively parallel PEs.”
DeepStore: In-Storage Acceleration for Intelligent Queries (2019, methodology): “Additional optimizations such as quantization, weight pruning [49, 103, 105], data-flow optimizations [29, 44, 65] are discussed to speed up the computation and improve energy efficiency.”
Planaria: Dynamic Architecture Fission for Spatial Multi-Tenant Acceleration of Deep Neural Networks (2020, background): “The need for higher speed and efficiency in DNN execution has led to an explosion of DNN accelerators [1, 3, 71–93] that has even made their way to operational datacenters (Google’s TPU [1], NVIDIA T4 [2], Microsoft Brainwave [3], etc.”
Angel-Eye: A Complete Design Flow for Mapping CNN Onto Embedded FPGA (2018, background): “Latest accelerator designs [33]–[35] is focusing on sparsity to achieve higher energy efﬁciency.”
Eyeriss v2: A Flexible Accelerator for Emerging Deep Neural Networks on Mobile Devices (2018, background): “Cnvlutin [39] only supports skipping cycles for activations and does not compress the weights, while Cambricon-X [40] does not keep activations in compressed form.”
Timeloop: A Systematic Approach to DNN Accelerator Evaluation (2019, background): “To provide high performance and energy efficiency to this class of compute-intensive algorithms, many DNN hardware accelerators have been proposed [1], [2], [5], [6], [12], [13], [15], [18], [25], [29], [33], [35], [39].”
MnnFast: A Fast and Scalable System Architecture for Memory-Augmented Neural Networks (2019, background): “can negate the pruning benefits; thus, accelerators specialized for sparse matrices [29, 31, 37, 40, 52, 88] are proposed.”
SIGMA: A Sparse and Irregular GEMM Accelerator with Flexible Interconnects for DNN Training (2020, methodology): “We compare SIGMA against other state-of-the-art accelerators: TPU [4], EIE [19], SCNN [33], OuterSPACE [32], Eyeriss v2 [11], Packed Systolic [26], and Cambricon-X [47].”
Efficient Acceleration of Deep Learning Inference on Resource-Constrained Edge Devices: A Review (2023, methodology): “An example of static sparsity involves the locations of zero weight being known beforehand for inference in Cambricon-X [233].”
Compressing DMA Engine: Leveraging Activation Sparsity for Training Deep Neural Networks (2017, background): “A series of accelerator designs have also been proposed for CNNs recently [23], [24], [25], [26], [27], [28], [29], [13], [14], [15].”