High-Temperature Performance of Silicon Junctionless MOSFETs

By Chi-Woo Lee, A. Borne, Isabelle Ferain, A. Afzalian, Ran Yan, N. Akhavan, P. Razavi, J. Colinge. IEEE Transactions on Electron Devices, 2010

399 citations recorded by the source corpus.

Subfields: Biomedical Engineering, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/f3d34c8f64d17c2bc018886778c5e872e3252034

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Citations in the corpus

RF Performance and Small-Signal Parameter Extraction of Junctionless Silicon Nanowire MOSFETs (2011, background): “solutions for these challenges, junctionless (JL) MuGFETs have been proposed as a novel structure to make a breakthrough for the junction-induced design issues [22]–[25].”
Effect of Band-to-Band Tunneling on Junctionless Transistors (2012, background): “[15], effects of strain on JLT performance [16], ballistic transport at short channel lengths [17], and radio-frequency performance analysis [18].”
A Junctionless Nanowire Transistor With a Dual-Material Gate (2012, background): “2192499 ied [1]–[3], and it has been demonstrated that junctionless”
A Quasi-Two-Dimensional Threshold Voltage Model for Short-Channel Junctionless Double-Gate MOSFETs (2012, background): “B EING SUPERIOR to conventional junction-based (JB) MOSFETs, junctionless (JL) MOSFETs without the junction between the source/drain and channel [1], [2] can be efficiently scaled into a nanometer regime for VLSI.”
Modeling and Simulation Investigation of Sensitivity of Symmetric Split Gate Junctionless FET for Biosensing Application (2017, background): “[18], mentioned advantages of Junctionless MOSFET such as simple fabrication process, low gate leakage current and low DIBL than conventional MOSFET [19], [20].”
Theory of the Junctionless Nanowire FET (2011, methodology): “The fabricated devices exhibit excellent turn-on and output characteristics [16], [17] with a nearly ideal SS 60 mV/dec, a large ON-current, which is quite comparable with that of an undoped channel transistor with the same geometry, a very small drain-induced barrier lowering (DIBL), and an interes”
Junctionless Multiple-Gate Transistors for Analog Applications (2011, background): “As mentioned in [14], the IDS–VGS characteristics of JL and IM transistors behave differently as a function of tem-”