Enabling the heterogeneous accelerator model on ultra-low power microcontroller platforms

By Francesco Conti, Daniele Palossi, Andrea Marongiu, Davide Rossi, Luca Benini. 2016

24 citations recorded by the source corpus.

The stringent power constraints of complex microcontroller based devices (e.g. smart sensors for the IoT) represent an obstacle to the introduction of sophisticated functionality. Programmable accelerators would be extremely beneficial to provide the flexibility and energy efficiency required by fast-evolving IoT applications; however, the integration complexity and sub-10mW power budgets have been considered insurmountable obstacles so far. In this paper we demonstrate the feasibility of coupling a low power microcontroller unit (MCU) with a heterogeneous programmable accelerator for speeding-up computation-intensive algorithms at an ultra-low power (ULP) sub-10mW budget. Specifically, we develop a heterogeneous architecture coupling a Cortex-M series MCU with PULP, a programmable accelerator for ULP parallel computing. Complex functionality is enabled by the support for offloading parallel computational kernels from the MCU to the accelerator using the OpenMP programming model. We prototype this platform using a STM Nucleo board and a PULP FPGA emulator. We show that our methodology can deliver up to 60× gains in performance and energy efficiency on a diverse set of applications, opening the way for a new class of ULP heterogeneous architectures.

Subfields: Electrical and Electronic Engineering, Hardware and Architecture

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Citations in the corpus

A 64-mW DNN-Based Visual Navigation Engine for Autonomous Nano-Drones (2018, methodology): “Similarly to what has been presented in [36], the PULPShield embodies the Host-Accelerator architectural paradigm, where the CF’s MCU offloads the intensive visual navigation workload to the PULP accelerator.”