Low subthreshold slope in junctionless multigate transistors

By Chi-Woo Lee, A. Nazarov, Isabelle Ferain, N. Akhavan, Ran Yan, P. Razavi, R. Yu, R. Doria, Jean-Pierre Colinge. 2010

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Charge-Plasma Based Process Variation Immune Junctionless Transistor (2014, background): “Although, JLT shows better electrical properties such as reduced short channel effects (SCEs), low OFF current [1]–[5], but variability is high due to random dopant fluctuation (RDF) and it is projected to be a serious problem when scaled to nanoscale dimensions [6]–[8].”
RF Performance and Small-Signal Parameter Extraction of Junctionless Silicon Nanowire MOSFETs (2011, unknown): “of doping techniques and thermal budget [22]–[24].”
Low-Voltage Tunnel Transistors for Beyond CMOS Logic (2010, unknown): “Bennett [9] later showed that universal computation can be done with time-reversible (or energyconserving) logic devices, so that the kT lnð2Þ dissipation, associated with erasure of information, can be avoided.”
Effect of Band-to-Band Tunneling on Junctionless Transistors (2012, background): “[19]; and 5) mobility enhancement due to bulk conduction [16].”
Simple Analytical Bulk Current Model for Long-Channel Double-Gate Junctionless Transistors (2011, background): “In addition, short-channel effects are more effectively suppressed [1]–[6] in comparison with their counterpart enclosing conventional junctions.”