Multiple-gate SOI MOSFETs: device design guidelines

By J. T. Park, Jean-Pierre Colinge. 2002

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Modeling and Simulation Investigation of Sensitivity of Symmetric Split Gate Junctionless FET for Biosensing Application (2017, methodology): “In order to reduce this impact, numerous multigate devices have been proposed such as Double Gate (DG) MOSFET, Surrounding-Gate/Gate All Around (SG/GAA) MOSFET and Fin-FETs, which can suppress the SCEs and improve gate controllability [16], [17].”
Modeling of nanoscale gate-all-around MOSFETs (2004, background): “The proposed model is valid for “well-tempered” GAA-MOSFETs; i.e., for transistors with small SCEs.”
High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices (2006, background): “Besides theoretical studies [15], [16], there have been several experimental attempts (although several of them suffer in gate definition) that demonstrated the advantages of GAA, or near”