AES implementation on a grain of sand
By Martin Feldhofer, Johannes Wolkerstorfer, Vincent Rijmen. 2005
438 citations recorded by the source corpus.
Subfields: Artificial Intelligence, Computer Vision and Pattern Recognition, Hardware and Architecture
View Paper: https://www.semanticscholar.org/paper/c4faa9d020b809a67f79b288d5d1cd3e8426a683
How researchers see this paper
The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.
In Artificial Intelligence
- Axel York Poschmann
- Christof Paar
- Subhadeep Banik
- Kyoji Shibutani
- Toru Akishita
- Harunaga Hiwatari
- Takanori Isobe
- San Ling
In Computer Vision and Pattern Recognition
- Axel York Poschmann
- San Ling
- Zheng Gong
- Svetla Nikova
- Andrey Bogdanov
- Amir Moradi
- Timo D. Hämäläinen
- Huaxiong Wang
In Hardware and Architecture
- Thomas Eisenbarth
- Svetla Nikova
- Gregor Leander
- Axel York Poschmann
- Christof Paar
- Sandeep S. Kumar
- Roel Maes
Citations in the corpus
- A Survey of Lightweight-Cryptography Implementations (2007, methodology): “However, researchers have described a low-power, low-cost AES implementation that requires only 3,400 gate equivalents (GEs) and encrypts a plaintext within 1,032 clock cycles.(3) This impressive result seems to have achieved the limit in area minimization.”
- New Lightweight DES Variants (2007, methodology): “The implementation requires also about 86% fewer clock cycles for encrypting of one block than the serialized AES implementation in [FWR05](1032 cycles vs.”
- RECTANGLE: a bit-slice lightweight block cipher suitable for multiple platforms (2015, neutral): “At size size Block (µm) (GE) 100 kHz (kbps) Block Ciphers AES-128 [43] 128 128 226 0.13 2400 56.6 LED-64 [6] 64 64 1248 0.18 966 5.1 PICCOLO-80 [7] 80 64 27 0.13 1496 237 PRESENT-80 [44] 80 64 32 0.18 1570 200 RECTANGLE-80 80 64 26 0.13 1599.5 246 RECTANGLE-128 128 64 26 0.13 2063.5 246 Stream Ciphe”
- Design and Implementation of Low-Area and Low-Power AES Encryption Hardware Core (2006, background): “According to our knowledge, only two 8-bit AES ASICs have previously been reported in the academic literature [4] [5].”
- HIGHT: A New Block Cipher Suitable for Low-Resource Device (2006, background): “In case of 8-bit oriented software implementation, HIGHT is far faster than AES.”
- Pushing the Limits: A Very Compact and a Threshold Implementation of AES (2011, methodology): “Low-power low-area implementations of the AES have been reported in [15] requiring 3100 GE and 160 clock cycles and in [13] requiring 3400 GE and 1032 clock cycles.”
- KATAN and KTANTAN - A Family of Small and Efficient Hardware-Oriented Block Ciphers (2009, neutral): “AES-128 [8] 128 128 3400 7.”
- Midori: A Block Cipher for Low Energy (2015, background): “The past few years have seen several low-power/area architectures for AES being reported in literature [28,31,18].”
- KLEIN: A New Family of Lightweight Block Ciphers (2010, background): “But for resourceconstrained devices, AES could be too expensive, despite the various approaches that have been proposed to reduce the costs of AES hardware and software implementations [20,24,25,31].”