Eyeriss v2: A Flexible Accelerator for Emerging Deep Neural Networks on Mobile Devices

By Yu-hsin Chen, Tien-Ju Yang, Joel S. Emer, Vivienne Sze. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2018

1,023 citations recorded by the source corpus.

A recent trend in deep neural network (DNN) development is to extend the reach of deep learning applications to platforms that are more resource and energy-constrained, e.g., mobile devices. These endeavors aim to reduce the DNN model size and improve the hardware processing efficiency and have resulted in DNNs that are much more compact in their structures and/or have high data sparsity. These compact or sparse models are different from the traditional large ones in that there is much more variation in their layer shapes and sizes and often require specialized hardware to exploit sparsity for performance improvement. Therefore, many DNN accelerators designed for large DNNs do not perform well on these models. In this paper, we present Eyeriss v2, a DNN accelerator architecture designed for running compact and sparse DNNs. To deal with the widely varying layer shapes and sizes, it introduces a highly flexible on-chip network, called hierarchical mesh, that can adapt to the different amounts of data reuse and bandwidth requirements of different data types, which improves the utilization of the computation resources. Furthermore, Eyeriss v2 can process sparse data directly in the compressed domain for both weights and activations and therefore is able to improve both processing speed and energy efficiency with sparse models. Overall, with sparse MobileNet, Eyeriss v2 in a 65-nm CMOS process achieves a throughput of 1470.6 inferences/s and 2560.3 inferences/J at a batch size of 1, which is $12.6\times $ faster and $2.5\times $ more energy-efficient than the original Eyeriss running MobileNet.

Subfields: Computer Vision and Pattern Recognition, Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/0682bfa5cca15726aab6c00ecfac91eb44379626

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Citations in the corpus

Planaria: Dynamic Architecture Fission for Spatial Multi-Tenant Acceleration of Deep Neural Networks (2020, background): “Eyeriss v2 [54] proposes a hierarchical architecture equipped with a flexible mesh-based NoC that provides flexibility to adapt to various level of data reuse.”
Efficient Acceleration of Deep Learning Inference on Resource-Constrained Edge Devices: A Review (2023, methodology): “Eyeriss v2 [237] uses the CSC format to store compressed parameters and activations.”
Sponge Examples: Energy-Latency Attacks on Neural Networks (2020, neutral): “As we discuss later, custom and semi-custom hardware often exploit sparsity in data and the adequacy of lowprecision computations to train neural networks, reducing both arithmetic complexity and DRAM accesses, and thus achieving significantly better power efficiency [18, 19].”
Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration (2019, background): “erators with different performance and energy efficiency targets for different applications across a diverse set of deployment scenarios [1], [12]–[14].”
Model Compression and Hardware Acceleration for Neural Networks: A Comprehensive Survey (2020, background): “A variety of compression techniques have been considered in the design of DNN accelerators at the cost of certain accuracy loss [10]–[13].”
Rigging the Lottery: Making All Tickets Winners (2019, background): “…to improve the performance of sparse networks on current hardware (Hong et al., 2019; Merrill & Garland, 2016), and new types of hardware accelerators will have better support for parameter sparsity (Wang et al., 2018; Mike Ashby, 2019; Liu et al., 2018; Han et al., 2016a; Chen et al., 2019).”
SIGMA: A Sparse and Irregular GEMM Accelerator with Flexible Interconnects for DNN Training (2020, methodology): “Eyeriss v2 [11] Limited weight dist.”