HardFails: Insights into Software-Exploitable Hardware Bugs
By Ghada Dessouky, David Gens, Patrick Haney, Garrett Persyn, Arun Karthik Kanuparthi, Hareesh Khattri, Jason M. Fung, Ahmad-Reza Sadeghi, Jeyavijayan Rajendran. 2019
158 citations recorded by the source corpus.
How researchers see this paper
The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.
- Shailja Thakur
- Siddharth Garg
- Jason Blocklove
- Baleegh Ahmad
- Hammond A. Pearce
- Ramesh Karri
- Brendan Dolan-Gavitt
- Benjamin Tan
Citations in the corpus
- Asleep at the Keyboard? Assessing the Security of GitHub Copilot’s Code Contributions (2021, neutral): “As such, they frequently require additional context (assets) beyond what is provided with the hardware definition directly [25].”
- An Empirical Cybersecurity Evaluation of GitHub Copilot's Code Contributions (2021, background): “As such, they frequently require additional context (assets) beyond what is provided with the hardware definition directly [24].”
- VeriGen: A Large Language Model for Verilog Code Generation (2023, background): “Digital hardware design flows involve designers writing code in hardware description languages (HDLs) such as Verilog and VHDL to specify hardware architectures and behaviors, a process that is both time-consuming and bugprone [7].”
- Chip-Chat: Challenges and Opportunities in Conversational Hardware Design (2023, methodology): “The process of translating these into the appropriate HDL (e.g. Verilog) must be done by hardware engineers, which is both time-consuming and error-prone [4].”