Minitaur, an Event-Driven FPGA-Based Spiking Network Accelerator

By Daniel Neil, Shih-Chii Liu. 2014

246 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

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In Electrical and Electronic Engineering

Citations in the corpus

A Survey of Neuromorphic Computing and Neural Networks in Hardware (2017, unknown): “[211], [264], [267], [290], [297], [316], [395], [491], [557],”
Deep Learning With Spiking Neurons: Opportunities and Challenges (2018, methodology): “Although this is clearly a sub-optimal use of SNNs, the method is eﬀective in practice and can be realized in hardware (Neil and Liu, 2014; Stromatias et al., 2015; Schmitt et al., 2017).”
Fast-classifying, high-accuracy spiking deep networks through weight and threshold balancing (2015, methodology): “This has been driven both by the interest to build more biologically realistic neural network models, and by recent improvements and the availability of larger-scale neuromorphic computing platforms, which are optimized for emulating brain-like spike-based computation in dedicated analog or digital ”
Supervised Learning Based on Temporal Coding in Spiking Neural Networks (2016, background): “Compared to rate-based networks, the networks we present can be implemented more efficiently on neuromorphic architectures where power consumption decreases as spike rates are reduced [7, 8, 9].”
Effective sensor fusion with event-based sensors and deep network architectures (2016, methodology): “The combination of spiking deep networks together with event-based sensors has been considered in previous studies, for a example, through a spiking CNN receiving DVS spikes [5], [6].”
Unsupervised learning of digit recognition using spike-timing-dependent plasticity (2015, methodology): “(2) training a rate-based neural network with backpropagation [20] (or other rate-based learning algorithms) and using those weights for an SNN, which we will call “rate-based learning” [8, 21, 22, 23].”
Memory and Information Processing in Neuromorphic Systems (2015, methodology): “This network architecture has been implemented on a Xilinx Spartan-6 LX150 FPGA [43] with very similar classification performance results (92”