CONV-SRAM: An Energy-Efficient SRAM With In-Memory Dot-Product Computation for Low-Power Convolutional Neural Networks

By Avishek Biswas, Anantha P. Chandrakasan. IEEE Journal of Solid-State Circuits, 2019

323 citations recorded by the source corpus.

This paper presents an energy-efficient static random access memory (SRAM) with embedded dot-product computation capability, for binary-weight convolutional neural networks. A 10T bit-cell-based SRAM array is used to store the 1-b filter weights. The array implements dot-product as a weighted average of the bitline voltages, which are proportional to the digital input values. Local integrating analog-to-digital converters compute the digital convolution outputs, corresponding to each filter. We have successfully demonstrated functionality (>98% accuracy) with the 10 000 test images in the MNIST hand-written digit recognition data set, using 6-b inputs/outputs. Compared to conventional full-digital implementations using small bitwidths, we achieve similar or better energy efficiency, by reducing data transfer, due to the highly parallel in-memory analog computations.

Subfields: Computer Vision and Pattern Recognition, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/a6d26a1478ce23b3b3a9df8eb37a85fdb1074893

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Citations in the corpus

Edge Computing with Artificial Intelligence: A Machine Learning Perspective (2022, methodology): “A static random access memory (SRAM) [102] is able to reduce memory data throughput, and it combines parallel CNNs to enable simultaneous access to different memory blocks.”
In-Memory Computing: Advances and prospects (2019, background): “, [13] requires adopting a 10-T bit cell, and [14] requires multiple memory-operation cycles).”
Hardware implementation of memristor-based artificial neural networks (2024, unknown): “The proposed circuit comprises 4 kb synapses fabricated in a 65 nm CMOS processand reported anenergy ef ﬁ ciencyof 55.8 TOPS per W. Incases where x is non-binary, one approach is to employ capacitors in addition to the SRAM cells 76,77,79 , involving a three-step process.”
A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference (2022, background): “Although the SRAM-based accelerator presented in another work 24 has a higher energy efficiency as well as throughput density, it requires the use of an off-chip weight buffer to store the total weight data of a network, leading to additional The LSTM unit comprises an input gate that receives the e”
Accurate deep neural network inference using computational phase-change memory (2019, methodology): “Various implementations such as switched-capacitor circuits 6 , charge-based 7 and current-based 8,9 computational circuits have been proposed and could demonstrate 1-bit arithmetic energy efﬁciencies of > 100 TOPS/W for matrix-vector multiplications 6,7 .”