Nonlinear thermal stress/strain analyses of copper filled TSV (through silicon via) and their flip-chip microbumps
By C. Selvanayagam, John H. Lau, Xiaowu Zhang, S. Seah, K. Vaidyanathan, T. Chai. Electronic Components and Technology Conference, 2008
143 citations recorded by the source corpus.
Subfields: Biomedical Engineering, Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/addb8c84e2b899fb86b3ee58a8569a88c49e8317
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In Biomedical Engineering
In Electrical and Electronic Engineering
Citations in the corpus
- Thermal management of 3D IC integration with TSV (through silicon via) (2009, background): “There are many critical issues of 3D IC integration [1-14], e.”
- Evolution, challenge, and outlook of TSV, 3D IC integration and 3d silicon integration (2011, background): “16 Cu-filled TSV interposer acts like a stress relief (reliability) buffer for Moore’s law chips [1, 19, 29, 90]”
- TSV manufacturing yield and hidden costs for 3D IC integration (2010, background): “In the development of 3D IC integration, at least the following must be noted and understood: [1-41]”
- A study of thermo-mechanical stress and its impact on through-silicon vias (2008, background): “The initial step in developing a 3D copper interconnection is to model the physical interaction between silicon, dielectric isolation, copper diffusion barrier and electro-deposited copper interconnect [16].”