Reduced electric field in junctionless transistors

By Jean-Pierre Colinge, Chi-Woo Lee, Isabelle Ferain, N. Akhavan, Ran Yan, P. Razavi, R. Yu, A. Nazarov, R. Doria. 2010

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Junctionless Multiple-Gate Transistors for Analog Applications (2011, background): “A reduction of E(x) is observed when VGT is increased in JL devices, whereas an increase of the electric field is observed when the gate voltage is increased in IM transistors, as reported in [32].”
Junctionless Transistors: Physics and Properties (2011, background): “This strongly reduces the degradation of mobility when gate voltage is increased in the on state [5].”
RF Performance and Small-Signal Parameter Extraction of Junctionless Silicon Nanowire MOSFETs (2011, background): “solutions for these challenges, junctionless (JL) MuGFETs have been proposed as a novel structure to make a breakthrough for the junction-induced design issues [22]–[25].”
Sensitivity of Threshold Voltage to Nanowire Width Variation in Junctionless Transistors (2011, background): “in junctionless transistors would become small [9], the simulated results suggest that the comprehensive analysis of the VT fluctuation caused by both the RDF and Wsi variation is required.”