Vertical cell array using TCAT(Terabit Cell Array Transistor) technology for ultra high density NAND flash memory

By J. Jang, Hansoo Kim, W. Cho, Hoosung Cho, Jinho Kim, S. Shim, Younggoan Jang, Jae-Hun Jeong, Byoungkeun Son, Dong Woo Kim and 13 more. Symposium on VLSI Technology, 2006

418 citations recorded by the source corpus.

View Paper: https://www.semanticscholar.org/paper/a7f921d996cc3f756a7c4f1ad914a75aad8f75bf

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

1. Thomas Mikolajick
2. Shimeng Yu
3. Uwe Schroeder
4. Pai-Yu Chen
5. M. Pešić
6. E. Yurchuk
7. J. Muller
8. S. Muller

Citations in the corpus

• Emerging Memory Technologies: Recent Trends and Prospects (2016, background): “State-of-the-art two-dimensional (2D) NAND flash has been scaled down to around 15 nm in 2015, while the 3D stackable NAND flash is emerging [54], [55].”
• Charge-Trapping Phenomena in HfO2-Based FeFET-Type Nonvolatile Memories (2016, methodology): “Scaling below the 28-nm technology node can be continued by fabricating FeFETs in nonplanar configurations such as FinFET devices or 3-D memory array architectures [3], [4].”