Fabrication of a Nonvolatile Full Adder Based on Logic-in-Memory Architecture Using Magnetic Tunnel Junctions
By S. Matsunaga, J. Hayakawa, Shoji Ikeda, K. Miura, H. Hasegawa, T. Endoh, Hideo Ohno, T. Hanyu. 2008
339 citations recorded by the source corpus.
Subfields: Atomic and Molecular Physics, and Optics, Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/9e81a0b52924ecf9c404f63db44c1cc799849cc2
How researchers see this paper
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In Atomic and Molecular Physics, and Optics
- Juan G. Alzate
- Kang L. Wang
- Weisheng Zhao
- Claude Chappert
- Jacques-Olivier Klein
- Dafine Ravelosona
- Yue Zhang
- Zhaohao Wang
In Electrical and Electronic Engineering
- Weisheng Zhao
- Ian A. Young
- Jacques-Olivier Klein
- Kang L. Wang
- Dafine Ravelosona
- Yue Zhang
- Claude Chappert
- Hideo Ohno
Citations in the corpus
- Spintronics (2015, methodology): “…and prototypes have been presented, such as the novel magnetic flip-flop (MFF), magnetic full adder (MFA), and magnetic lookup table (MLUT) [Matsunaga et al. 2008; Ryu et al. 2012; Goncalves et al. 2013; Zhao et al. 2014], etc. Figure 22 shows an example of our proposed 1-bit MFA circuit…”
- High Speed, High Stability and Low Power Sensing Amplifier for MTJ/CMOS Hybrid Logic Circuits (2009, methodology): “later [12] and used for realizing a non volatile full adder [17].”
- Electric-Field-Controlled Magnetoelectric RAM: Progress, Challenges, and Scaling (2015, background): “, in embedded cache or logic-in-memory architectures [18], [19].”
- Proposal of a Spin Torque Majority Gate Logic (2010, background): “have a spin degree of freedom involved in their operation: the Datta-Das spin modulator [4], the spin field-effect transistor [5], and the magnetic-tunnel-junction-based logic [6]–[9].”
- Spin-transfer torque RAM technology: Review and prospect (2012, background): “25b shows an example of basic-cell level example [52], where a full adder with a non-volatile storage cell was designed and demonstrated with a shown chip.”
- Overview of Beyond-CMOS Devices and a Uniform Methodology for Their Benchmarking (2013, background): “d FET [44]; magnetic domain-wall Logic [45]; domain wall majority gate logic [46]; MottFET [47]; spin Hall effect transistor [48]; few spin device [49]; magnetic tunnel junction (MTJ) plus CMOS logic [50,51,52,53]. We also do not cover the optoelectronic excitonic transistor, which was demonstrated ”