Interconnection Networks: An Engineering Approach

By J. Duato, Sudhakar Yalamanchili, Ni Lionel. 2002

2,158 citations recorded by the source corpus.

View Paper: https://www.semanticscholar.org/paper/80791021a29ac4e353efe804cef4b835b340bf49

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Citations in the corpus

Performance evaluation and design trade-offs for network-on-chip interconnect architectures (2005, background): “The Torus architecture is basically the same as a regular mesh [22]; the only difference is that the switches at the edges are connected to the switches at the opposite edge through wrap-around channels.”
Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives (2009, background): “, turn model routing and planar adaptive routing [39], [45])”
BCube: a high performance, server-centric network architecture for modular data centers (2009, background): “Though network interconnections have been studied for decades [11, 18], to the best of our knowledge, none of the previous structures meets the MDC requirements and the physical constraint that servers can only have a small number of network ports.”
Dcell: a scalable and fault-tolerant network structure for data centers (2008, background): “Fat Tree [6] overcomes the bottleneck degree problem by introducing more bandwidth into the switches near the root.”
Towards predictable datacenter networks (2011, background): “For example, many topologies have been studied for HPC platforms, such as multi-dimensional cubes, hypercube and its variants, and even more complex topologies such as Butterfly networks, de Bruijn, etc [11].”
"It's a small world after all": NoC performance optimization via long-range link insertion (2006, background): “…traffic patterns characterized by the communication frequencies, can be written as (6) where is the distance between router and router , and , , and are the architectural parameters representing the time needed to make the routing decision, traverse the switch and the link, respectively [14].”
Token Coherence: decoupling performance and correctness (2003, methodology): “Messages are multiplexed over a single shared interconnect using virtual networks and channels, and broadcast messages use bandwidth-efficient treebased multicast routing [ 14, section 5.5 ].”
HERMES: an infrastructure for low area overhead packet-switching networks on chip (2004, methodology): “This leads to the concept of packet [12].”
System-level power optimization: techniques and tools (2000, background): “In constrast, channel allocation and multiple access control have been studied in detail for shared system busses, where several computations and storage must communicate over the same channel [Duato et al. 1997].”
Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation (2009, unknown): “We assume wormhole routing [20] as the data transport mechanism where the packet is divided into fixed length flow control units or flits.”
Slim Fly: A Cost Effective Low-Diameter Network Topology (2014, methodology): “We use a strategy similar to the one introduced by Gopal [17], [21].”
Data Center Networks (2013, unknown): “Helios uses an algorithm from Hedera [3] to estimate traffic demand between racks.”
Xpipes: a network-on-chip architecture for gigascale systems-on-chip (2004, background): “Three policies are feasible in this context [33].”
3-D Topologies for Networks-on-Chip (2006, background): “The architecture of the router is considered here to be a canonical router with input and output buffering [15].”