Malware Guard Extension: Using SGX to Conceal Cache Attacks

By Michael Schwarz, Samuel Weiser, Daniel Gruss, Clémentine Maurice, Stefan Mangard. 2017

448 citations recorded by the source corpus.

In modern computer systems, user processes are isolated from each other by the operating system and the hardware. Additionally, in a cloud scenario it is crucial that the hypervisor isolates tenants from other tenants that are co-located on the same physical machine. However, the hypervisor does not protect tenants against the cloud provider and thus the supplied operating system and hardware. Intel SGX provides a mechanism that addresses this scenario. It aims at protecting user-level software from attacks from other processes, the operating system, and even physical attackers.

Subfields: Artificial Intelligence, Information Systems, Signal Processing

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Citations in the corpus

Ekiden: A Platform for Confidentiality-Preserving, Trustworthy, and Performant Smart Contracts (2018, neutral): “Although trusted hardware aims to protect confidentiality for TEE, recent work has uncovered data leakage via side-channel attacks [18, 38, 40, 46, 53, 54, 66, 70, 79, 91, 93].”
Komodo: Using verification to disentangle secure-enclave hardware from software (2017, background): “Schwarz et al. [76] observed that existing hardware support for cache partitioning (Intel cache allocation technology [63]) could defeat such attacks, if only it were activated on enclave entry, but this is not a feature that SGX presently provides.”
SGX-Bomb: Locking Down the Processor via Rowhammer Attack (2017, background): “Many sidechannels attacks exploiting page fault [7, 32, 37], cache timing [6, 13, 16, 30], and branch prediction [24] have been proposed to attack SGX.”
Another Flip in the Wall of Rowhammer Defenses (2017, methodology): “Furthermore, enclaves are excluded from the CPU performance counters [64].”
SgxPectre Attacks: Leaking Enclave Secrets via Speculative Execution (2018, methodology): “GX. The SgxPectre Attacks are variants of micro-architectural side-channel attacks. Previously, various micro-architectural side-channel attacks have been demonstrated on SGX, which CPU cache attacks [7, 19, 21, 60], BTB attacks [44], page-table attacks [64, 74, 82], cache-DRAM attacks [77], etc. Sg”
ROTE: Rollback Protection for Trusted Execution (2017, background): “We consider information leakage from side-channel attacks a realistic threat [17, 18, 19], but an orthogonal problem to rollback attacks, and thus outside of our model.”
Plundervolt: Software-based Fault Injection Attacks against Intel SGX (2020, background): “However, this is actually a standard scenario in classical side-channel attack works, which accurately reconstruct enclave control flow by, for instance, monitoring page table access patterns [78, 73], cache accesses [58] or interrupt counts [71, 72].”
Software Grand Exposure: SGX Cache Attacks Are Practical (2017, background): “Recently, a number of cache-based attacks targeted SGX platforms [44, 38, 19].”
IRON: Functional Encryption using Intel SGX (2017, background): “For instance, several side-channel attacks have come to light since SGX’s initial release [13, 38, 52, 58, 59].”
CacheZoom: How SGX Amplifies The Power of Cache Attacks (2017, background): “An enclave-to-enclave attack through LLC in a different adversarial scenario [46], as well as methods to detect privileged side-channel attacks from within an enclave [16] have concurrently been proposed.”
High-Resolution Side Channels for Untrusted Operating Systems (2017, methodology): “Several recent papers study cache side channels for enclaves using techniques that are different from ours and focusing primarily on crypto targets [12, 23, 40].”
SgxPectre: Stealing Intel Secrets from SGX Enclaves Via Speculative Execution (2018, background): “Previously, various micro-architectural side-channel attacks have been demonstrated on SGX, which CPU cache attacks [7, 19, 21, 60], BTB attacks [44], page-table attacks [64, 74, 82], cache-DRAM attacks [77], etc .”
An Algorithmic Framework For Differentially Private Data Analysis on Trusted Processors (2018, background): “) As a result, accesses leaked through memory side-channels 4 undermine the confidentiality promise of enclaves [55, 49, 30, 35, 17, 12, 38].”
ZombieLoad: Cross-Privilege-Boundary Data Sampling (2019, background): “Specifically, microarchitectural elements often do not distinguish between different applications or privilege levels [9, 14, 37, 45, 58, 61, 63].”