Efficient Rijndael Encryption Implementation with Composite Field Arithmetic

By Atri Rudra, Pradeep K. Dubey, Charanjit S. Jutla, Vijay Kumar, Josyula R. Rao, Pankaj Rohatgi. Workshop on Cryptographic Hardware and Embedded Systems, 2001

312 citations recorded by the source corpus.

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

A Very Compact S-Box for AES (2005, methodology): “One approach to using these two forms, as suggested by [13], is to convert each byte of the input block once, and do all of the AES algorithm in the new form, only converting back at the end of all the rounds.”
Error Analysis and Detection Procedures for a Hardware Implementation of the Advanced Encryption Standard (2003, background): “Industrial Days Giornate di Matematica per l’Industria Milan, 1 December 2003”
Efficient Cache Attacks on AES, and Countermeasures (2010, background): “For AES, bitsliced implementation on popular architectures can offer a throughput comparable to that of lookup-based implementations [52][34][51][35][31][26], but only when several independent blocks are processed in parallel.”
Very Compact FPGA Implementation of the AES Algorithm (2003, methodology): “Various area efficient implementations of AES S-boxes were proposed in [2] [4] [6] [8] [10] [13] [22] [23] [31].”
A Compact Rijndael Hardware Architecture with S-Box Optimization (2001, methodology): “Reference [16] proposed the use of composite field arithmetic to reduce the computation cost of the S-Box, but no detailed hardware implementation was provided.”