Program optimization space pruning for a multithreaded gpu
By Shane Ryoo, Christopher I. Rodrigues, Sam S. Stone, Sara S. Baghsorkhi, Sain-Zee Ueng, John A. Stratton, Wen-mei W. Hwu. IEEE/ACM International Symposium on Code Generation and Optimization, 2008
316 citations recorded by the source corpus.
Subfields: Computer Networks and Communications, Hardware and Architecture
View Paper: https://www.semanticscholar.org/paper/41bff2e236e73c5c9b21f8660856f58bba46aaf5
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In Computer Networks and Communications
- Tor M. Aamodt
- Onur Mutlu
- Saugata Ghose
- Adwait Jog
- Sunpyo Hong
- Hyesoon Kim
- Phillip B. Gibbons
- Gennady Pekhimenko
In Hardware and Architecture
- Tor M. Aamodt
- Onur Mutlu
- Saugata Ghose
- Adwait Jog
- Albert Cohen
- Sunpyo Hong
- Hyesoon Kim
- Phillip B. Gibbons
Citations in the corpus
- OpenMP to GPGPU: a compiler framework for automatic translation and optimization (2009, methodology): “Several studies have been conducted to optimize the performance of CUDA-based GPGPU applications; an optimization space pruning technique [15] has been proposed, using a Pareto-optimal curve, to find the optimal configuration for a GPGPU application.”
- Polyhedral parallel code generation for CUDA (2013, methodology): “have shown that the optimization space for CUDA programs can be highly non-linear, and highly challenging for model-based heuristics, performance modeling, or feedback-directed methods [Ryoo et al. 2008b; Ryoo et al. 2008a].”
- Zorua: A holistic approach to resource virtualization in GPUs (2016, methodology): “For a naive programmer, this is a challenging task [14, 47, 59, 60, 61, 65] because, in addition to selecting a specification suited to an algorithm, the programmer needs to be aware of the details of the GPU architecture to fit the specification to the underlying hardware resources.”
- An analytical model for a GPU architecture with memory-level and thread-level parallelism awareness (2009, background): “[24] proposed two metrics to reduce optimization spaces for programmers by calculating utilization and efficiency of applications.”
- Analyzing CUDA workloads using a detailed GPU simulator (2009, background): “Thread scheduling inside a shader core is performed with zero overhead on a fine-grained basis.”