Implementing Synaptic Plasticity in a VLSI Spiking Neural Network Model

By Johannes Schemmel, Andreas Grübl, K. Meier, Eilif B. Muller. 2006

164 citations recorded by the source corpus.

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

A wafer-scale neuromorphic hardware system for large-scale neural modeling (2010, methodology): “This is similar to the implementation described in [8].”
Phenomenological models of synaptic plasticity based on spike timing (2008, background): “c Reduced symmetric interpretation: as in c but only for immediate pairings (Burkitt et al. 2004: Model IV, also implemented in hardware by Schemmel et al. 2006 )”
Spin-torque building blocks. (2014, background): “However, CMOS implementations of neural networks typically require static random access memoriy (SRAM) banks to store the synapse weights, plus tens of transistors to mimic their plasticity [95].”
Finding a roadmap to achieve large neuromorphic hardware systems (2013, background): “Table 1 shows the structure presented in this paper results in the best synaptic density over other ICs built to date (Indiveri et al., 2006; Schemmel et al., 2006, 2008b; Camilleri et al., 2007; Brink et al., 2012).”
Neuromorphic Silicon Neuron Circuits (2011, background): “Figure 17A shows an exemplary neuron circuit which is part of a 100k synapse network chip (Schemmel et al., 2006).”