A wafer-scale neuromorphic hardware system for large-scale neural modeling

By Johannes Schemmel, Daniel Brüderle, Andreas Grübl, Matthias Hock, K. Meier, S. Millner. Proceedings of 2010 IEEE International Symposium on Circuits and Systems, 2010

727 citations recorded by the source corpus.

Subfields: Artificial Intelligence, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/7c32e01d3b8511fe16d0bd1f385c43f95d2cc772

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Citations in the corpus

Noise as a Resource for Computation and Learning in Networks of Spiking Neurons (2014, background): “[72]) this would provide response times in the range of tens of microseconds.”
Event-driven contrastive divergence for spiking neuromorphic systems (2013, background): “Their implementation on neuromorphic hardware platforms emulating large-scale networks of spiking neurons can have significant advantages from the perspectives of scalability, power dissipation and real-time interfacing with the environment.”
A Survey of Neuromorphic Computing and Neural Networks in Hardware (2017, unknown): “[21], [408], [409], [428], [430]–[432], [440]–[444], [450],”
SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network Simulation (2013, background): “There is a significant body of existing and proposed work on the hardware implementation of neural networks using a wide variety of underlying technology: neuromorphic hardware [2], [3], mixed-signal VLSI [4], GPGPU systems [5], FPGA-based accelerator boards [6], nanotechnology [7], and combinations”
Long short-term memory and Learning-to-learn in networks of spiking neurons (2018, background): “The superior computing and learning capabilities of LSNNs suggest that they are also of interest for implementation in spike-based neuromorphic chips such as Brainscales [9], SpiNNaker [10], True North [2], chips from ETH Zürich [11], and Loihi [12].”
Neurogrid: A Mixed-Analog-Digital Multichip System for Large-Scale Neural Simulations (2014, methodology): “The Heidelberg University BrainScales project (HICANN chip) aims to reduce the number of transistors these electronic circuits require by using an analog approach [9].”
Deep Rewiring: Training very sparse deep networks (2017, background): “The situation is even more critical in neuromorphic hardware, where either hard upper bounds on network connectivity are unavoidable (Schemmel et al., 2010; Merolla et al., 2014) or fast on-chip memory of local processing cores is severely limited, for example the 96 MByte lo-cal memory of cores in…”
Neuro-Inspired Computing With Emerging Nonvolatile Memorys (2018, methodology): “BrainScaleS platform is based on HICANN chip in 180 nm node that use analog neurons similar as the leaky integrate-and-fire model and digital synapses made of 4-bit 6-transistor SRAM cells and 4-bit digitalanalog-converter (DAC) to interface with analog neurons [35].”
Neuromorphic computing with multi-memristive synapses (2017, background): “on Neural Networks (IJCNN), 1775–1781 (2011). 49Gütig, R., Aharonov, R., Rotter, S. & Sompolinsky, H. Learning input correlations through nonlinear temporally asymmetric hebbian plasticity. J. Neurosci. 23, 3697–3714 (2003). 50Tuma, T., Pantazi, A., Le Gallo, M., Sebastian, A. & Eleftheriou, E. Stoc”
Large-scale neuromorphic computing systems (2016, methodology): “Within a BrainScaleS wafer each of the 48 reticles holds eight High-Count Analogue Neural Network ( HiCANN ) die, each of which implements 512 adaptive exponential integrate and ﬁ re ( AdExp ) [ 21 ] neurons and over 100 000 synapses.”
The SpiNNaker Project (2014, methodology): “• The Heidelberg HICANN system [47] employs wafer-scale above threshold analog circuits that operate at 10(4)x biological real time using a twolayer AER protocol, one layer for intrawafer communication and a second layer for interwafer communication.”
A 0.086-mm$^2$ 12.7-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28-nm CMOS (2018, unknown): “Mixed-signal designs with core analog neuron and synapse computation and high-speed digital periphery are grouped on the left [23]–[25], [27], [63], [64], digital designs are grouped together with ODIN on the right [16], [28]–[31].”
Opportunities for neuromorphic computing algorithms and applications (2022, background): “The European Union’s Human Brain Project sponsored the development of SpiNNaker 6 and BrainScaleS 20 to enable neuroscience simulations at scale.”
The remarkable robustness of surrogate gradient learning for instilling complex function in spiking neural networks (2020, background): “…results suggest that most biological networks exhibit sparse spiking activity, a feature that is presumed to underlie their superior energy efficiency (Boahen, 2017; Cramer, Billaudelle et al., 2020; Neftci, 2018; Roy, Jaiswal, & Panda, 2019; Schemmel et al., 2010; Sterling & Laughlin, 2017).”
Deep Learning With Spiking Neurons: Opportunities and Challenges (2018, background): “The BrainScaleS system (Schemmel et al., 2010) and its successor (Aamir et al., 2018) is an especially promising candidate for on-chip learning due to its acceleration of up to a factor of 10000 compared to biological real time, but so far STDP is only shown for small networks on a prototype chip (P”
Spike-driven Transformer (2023, background): “Because of the choice that uses spiking neurons and synapses as basic units, neuromorphic chips [43–45, 2, 46, 3, 4] have unique features, such as highly parallel operation, collocated processing and memory, inherent scalability, and spike-driven computing, etc. Typical neuromorphic chips consume…”