Neuromorphic Silicon Neuron Circuits

By Giacomo Indiveri, B. Linares‐Barranco, T. Hamilton, A. van Schaik, Ralph Etienne-Cummings, Tobi Delbruck, Shih-Chii Liu, Piotr Dudek, P. Häfliger, S. Renaud and 10 more. 2011

1,751 citations recorded by the source corpus.

Hardware implementations of spiking neurons can be extremely useful for a large variety of applications, ranging from high-speed modeling of large-scale neural systems to real-time behaving systems, to bidirectional brain–machine interfaces. The specific circuit solutions used to implement silicon neurons depend on the application requirements. In this paper we describe the most common building blocks and techniques used to implement these circuits, and present an overview of a wide range of neuromorphic silicon neurons, which implement different computational models, ranging from biophysically realistic and conductance-based Hodgkin–Huxley models to bi-dimensional generalized adaptive integrate and fire models. We compare the different design methodologies used for each silicon neuron design described, and demonstrate their features with experimental results, measured from a wide range of fabricated VLSI chips.

Subfields: Cognitive Neuroscience, Electrical and Electronic Engineering

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Citations in the corpus

Deep learning in neural networks: An overview (2014, neutral): “Future energy-efficient hardware for DL in NNsmay implement aspects of such models (e.g., Fieres, Schemmel, & Meier, 2008; Glackin, McGinnity, Maguire, Wu, & Belatreche, 2005; Indiveri et al., 2011; Jin et al., 2010; Khan et al., 2008; Liu et al., 2001; Merolla et al., 2014; Neil & Liu, 2014; Roggen”
Organic electronics for neuromorphic computing (2018, background): “On the one hand, asynchronous spiking neural networks based on silicon neurons and synapses, consisting of multi-element circuits 4 , have been the focus of attention in emulating large-scale biological neural networks, as well as in event-driven computing 5 .”
Synaptic electronics: materials, devices and applications (2013, methodology): “We limit this review to solid-state devices for the emulation of the synaptic functionalities and do not cover the literature on neuromorphic circuits [14].”
Integration of nanoscale memristor synapses in neuromorphic computing architectures (2013, methodology): “as the ‘Adaptive Exponential’ (AdExp) I&F model [67, 49].”
On the Robustness of a Neural Network (2017, positive): “Recent progress in neuromorphic hardware brings such a solution, going beyond the Von Neumann paradigm (relying on logical circuits) and using electronic chips that are themselves neural networks [10], [11], [9], [12].”
The SpiNNaker Project (2014, background): “Analog models [45] may be subthreshold [46], whereupon biological real-time performance is achievable, or above threshold [47], where the circuits are likely to be much faster than biological real time.”
Event-driven contrastive divergence for spiking neuromorphic systems (2013, methodology): “ORIGINAL RESEARCH ARTICLE published: 30 January 2014 doi: 10.3389/fnins.2013.00272 Event-driven contrastive divergence for spiking neuromorphic systems Emre Neftci1*, Srinjoy Das1,2, Bruno Pedroni3, Kenneth Kreutz-Delgado1,2 and Gert Cauwenberghs1,3 1 Institute for Neural Computation, University of ”
An efficient automated parameter tuning framework for spiking neural networks (2014, background): “…spiking neural networks (SNNs), there are still many challenges to overcome before these neurobiologically inspired algorithms can be used in practical applications that can be deployed on neuro-morphic hardware (Boahen, 2005; Markram, 2006; Nageswaran et al., 2010; Indiveri et al., 2011).”
Fully memristive neural networks for pattern classification with unsupervised learning (2018, positive): “Progress has been made in building hardware ANNs that incorporate redox memristors 2–14 , phase-change memristors 15–18 , organic transistors 19 and conventional CMOS circuits 20,21 to emulate synapses by utilizing their tuneable conductance as synaptic weights.”
Deep Learning With Spiking Neurons: Opportunities and Challenges (2018, methodology): “…event representation (AER) protocol (Mahowald, 1994; Boahen, 2000), which is used to connect, e.g., event-based sensors (Lichtsteiner et al., 2008) via digital interconnect to neuromorphic chips (Indiveri et al., 2011; Amir et al., 2017) or digital post-processing hardware (Furber et al., 2014).”
Physics for neuromorphic computing (2020, background): “CMOS-based artificial neurons and synapses are typically several micrometers wide 16 , and the number of physical neurons and synapses that can be integrated in a CMOS chip is inherently limited by the chip area.”
An artificial spiking afferent nerve based on Mott memristors for neurorobotics (2020, background): “Recently, various technologies have been explored to build hardware SNNs, such as digital logic circuits 7,8 , complementary metal-oxide semi-conductor (CMOS) analog circuits 9,10 , and emerging memris-tors 11 – 13 .”