BSIM4 gate leakage model including source-drain partition

By K. Cao, W. Lee, Weidong Liu, X. Jin, P. Su, S. Fung, J. An, B. Yu, Chenming Hu. International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138), 2000

222 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/224efc8be41bc12e481b9519e9f98c953924f4ae

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Citations in the corpus

• Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits (2003, background): “In positive-channel MOSs (PMOSs), HVB controls the gate to channel leakage in inversion, whereas gate-to-body leakage is controlled by EVB in depletion-inversion and ECB in accumulation [31], [ 32 ].”
• Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods (2006, background): “For example, for relatively thin oxide thicknesses in the order of 2-3nm, at VGS=1V, every 0.2nm reduction in Tox causes a 10 fold increase in IG [ 16 ]].”
• Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits (2005, background): “2nm reduction in Tox causes a tenfold increase in IG [9].”
• Mobility measurement and degradation mechanisms of MOSFETs made with ultrathin high-k dielectrics (2004, background): “For a small , the gate leakage current, , is nearly unaffected by the small lateral field [28], and these two different s should cause a similar amount of .”