Improved sense-amplifier-based flip-flop: design and measurements

By B. Nikolić, V. Oklobdzija, Vladimir Marko Stojanovic, Wenyan Jia, J. Chiu, M. Leung. IEEE Journal of Solid-State Circuits, 2000

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A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time (2007, methodology): “1, have become especially popular [3-5] because of their high input impedance, full-swing output and absence of static power consumption.”
A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards (2002, methodology): “Transistor M1, which is always on, prevents a floating node by serving as a path for subthreshold currents, as it does in case of the original SAFF.”
Yield and speed optimization of a latch-type voltage sense amplifier (2004, background): “As a sense-amplifier-based flip-flop, the circuit has been reported to be one of the fastest flip-flops in state-of-the-art processors/VLSI designs [6], and can significantly reduce power”
CMOS Imager With 1024 SPADs and TDCs for Single-Photon Timing and 3-D Time-of-Flight (2014, background): “7: M1–M4 form a sense-amplifier based latch [31], M7 and M8 assure a fast recharge after commutation, M5 and M6 form a pseudo p-MOS NOR gate, which pre-charges both branches at the same level when no input is received.”
1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS (2006, methodology): “The delayed-clock replica vector is sampled by FREF using an array of 48 sense-amplifier-based flip-flops that are adapted from [13].”