1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS

By R. Staszewski, S. Vemulapalli, P. Vallur, J. Wallberg, P. Balsara. IEEE Transactions on Circuits and Systems - II - Express Briefs, 2006

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A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping (2009, background): “Digital Object Identifier 10.1109/JSSC.2009.2014709 an active research topic in the mixed-signal circuit community [5]–[10].”
A 9 b, 1.25 ps Resolution Coarse–Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue (2008, methodology): “A delay-locked loop (DLL) can be used to control the delay in the CTDC chain [1], [4], [9], [10], [12], or period estimation in the digital PLL [ 3 ] makes it possible to compensate the variation while it is operating.”
CMOS Imager With 1024 SPADs and TDCs for Single-Photon Timing and 3-D Time-of-Flight (2014, methodology): “Such ranges could be achieved through interpolation methods based for instance on Pulse-Shrinking delay line [23], Tapped delay line [24], or standard and cyclic Vernier delay line [25] elements.”
Be flexible (2008, background): “Literature provides several architectures and concepts for the feedback path [15]–[18].”