Silicon interposer with TSVs (Through Silicon Vias) and fine multilayer wiring

By M. Sunohara, T. Tokunaga, Takashi Kurihara, M. Higashi. Electronic Components and Technology Conference, 2008

157 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/0e8cf032d7318278f231161a04db5fbc0ee26278

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In Electrical and Electronic Engineering

1. John H. Lau

Citations in the corpus

• Low-Cost Thin Glass Interposers as a Superior Alternative to Silicon and Organic Interposers for Packaging of 3-D ICs (2012, background): “Although, silicon interposers are being developed to overcome these challenges [5], they face a”
• TSV manufacturing yield and hidden costs for 3D IC integration (2010, background): “In the development of 3D IC integration, at least the following must be noted and understood: [1-41]”
• Thermal management of 3D IC integration with TSV (through silicon via) (2009, background): “There are many critical issues of 3D IC integration [1-14], e.”