Differential Power Analysis in the Presence of Hardware Countermeasures

By Christophe Clavier, Jean-Sébastien Coron, Nora Dabbous. Workshop on Cryptographic Hardware and Embedded Systems, 2000

481 citations recorded by the source corpus.

Subfields: Artificial Intelligence, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/076949477707097976b7ea4f514caf15e4679817

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Citations in the corpus

Aegis: A Single-Chip Secure Processor (2007, background): “On the other hand, a more advanced technique called differential power analysis (DPA) uses subtle statistical correlations between the secret and the dissipated power [23, 62].”
Introduction to differential power analysis (2011, background): “(See [33] for additional details on why temporal noise is less effective.”
Fault Based Cryptanalysis of the Advanced Encryption Standard (AES) (2003, background): “In the basic fault model as well as in the probabilistic fault model, we always assumed that the attacker is able to exactly determine the time when he resets the value of a memory bit b. Unfortunately, as described in [ CCD ], some modern secure microcontrollers are equipped with a randomized timin”
Template Attacks (2002, background): “Since Paul Kocher’s original paper [12], a number of devastating attacks, such as Simple Power Analysis (SPA) and Differential Power Analysis (DPA) have been reported on a wide variety of cryptographic implementations [15,18, 6,11,17,8,3,4,10,16,7,5,21].”
A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards (2002, background): “Integration techniques, however, are able to resynchronize the power traces [3].”
Convolutional Neural Networks with Data Augmentation Against Jitter-Based Countermeasures - Profiling Attacks Without Pre-processing (2017, background): “In particular, if not treated with a proper realignment, it makes the PoI selection harder, obliging the attacker to consider a wide range of points for the characterization and matching (the more effective the misalignment, the wider the range), directly or after a previous integration [7] or a dim”
Side-Channel Attacks: Ten Years After Its Publication and the Impacts on Cryptographic Module Security Testing (2005, background): “However, the effect of these countermeasures can be reduced by various signal processing techniques ([84]).”
Correlation Power Analysis with a Leakage Model (2004, methodology): “It is generally assumed that the data leakage through the power side-channel depends on the number of bits switching from one state to the other [6, 8] at a given time.”
A Primer on Hardware Security: Models, Methods, and Metrics (2014, background): “It can be shown that decreasing the SNR of the side-channel information by a factor of K increases the number of required sidechannel samples by a factor of K(2) [96].”
Hardware Countermeasures against DPA ? A Statistical Analysis of Their Effectiveness (2004, background): “The classic countermeasure that is based on this principle is the insertion of random delays [3], which can even be implemented in software.”
Side-Channel Leakage of Masked CMOS Gates (2005, background): “styles with a data-independent power consumption [20, 21], noise generators and the insertion of random delays [4, 12].”