A scalable approach to thread-level speculation

By J. Steffan, Christopher B. Colohan, Antonia Zhai, Todd C. Mowry, Carnegie Mellon. Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201), 2000

411 citations recorded by the source corpus.

While architects understand how to build cost-effective parallel machines across a wide spectrum of machine sizes (ranging from within a single chip to large-scale servers), the real challenge is how to easily create parallel software to effectively exploit all of this raw performance potential. One promising technique for overcoming this problem is Thread-Level Speculation (TLS), which enables the compiler to optimistically create parallel threads despite uncertainty as to whether those threads are actually independent. In this paper we propose and evaluate a design for supporting TLS that seamlessly scales to any machine size because it is a straightforward extension of writeback invalidation-based cache coherence (which itself scales both up and down). Our experimental results demonstrate that our scheme performs well on both single-chip multiprocessors and on larger-scale machines where communication latencies are twenty times larger.

Subfields: Computer Networks and Communications, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/03b6c3abbb557f13fd5e37106854b809b5d028a8

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In Computer Networks and Communications

  1. Keshav Pingali
  2. Ravi Rajwar
  3. Håkan Grahn
  4. James R. Goodman
  5. Josep Torrellas
  6. Luis Ceze
  7. Martin Burtscher
  8. T. Harris

In Hardware and Architecture

  1. Keshav Pingali
  2. Ravi Rajwar
  3. Håkan Grahn
  4. James R. Goodman
  5. Josep Torrellas
  6. Luis Ceze
  7. Martin Burtscher
  8. T. Harris

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