A scalable approach to thread-level speculation
By J. Steffan, Christopher B. Colohan, Antonia Zhai, Todd C. Mowry, Carnegie Mellon. Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201), 2000
411 citations recorded by the source corpus.
While architects understand how to build cost-effective parallel machines across a wide spectrum of machine sizes (ranging from within a single chip to large-scale servers), the real challenge is how to easily create parallel software to effectively exploit all of this raw performance potential. One promising technique for overcoming this problem is Thread-Level Speculation (TLS), which enables the compiler to optimistically create parallel threads despite uncertainty as to whether those threads are actually independent. In this paper we propose and evaluate a design for supporting TLS that seamlessly scales to any machine size because it is a straightforward extension of writeback invalidation-based cache coherence (which itself scales both up and down). Our experimental results demonstrate that our scheme performs well on both single-chip multiprocessors and on larger-scale machines where communication latencies are twenty times larger.
Subfields: Computer Networks and Communications, Hardware and Architecture
View Paper: https://www.semanticscholar.org/paper/03b6c3abbb557f13fd5e37106854b809b5d028a8
How researchers see this paper
The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.
In Computer Networks and Communications
- Keshav Pingali
- Ravi Rajwar
- Håkan Grahn
- James R. Goodman
- Josep Torrellas
- Luis Ceze
- Martin Burtscher
- T. Harris
In Hardware and Architecture
- Keshav Pingali
- Ravi Rajwar
- Håkan Grahn
- James R. Goodman
- Josep Torrellas
- Luis Ceze
- Martin Burtscher
- T. Harris
Citations in the corpus
- Optimistic parallelism requires abstractions (2007, background): “More recent work has provided hardware support for this kind of coarse-grain loop-level speculation, now known as thread-level speculation (TLS) [36, 43].”
- Bulk Disambiguation of Speculative Threads in Multiprocessors (2006, background): “[11, 15, 17, 22, 23, 24, 26, 27]), threads are tasks from a sequential program.”
- Transactional lock-free execution of lock-based programs (2002, background): “SLE, like other proposals for speculation [48, 61, 154, 156], uses speculative store retirement.”
- The tao of parallelism in algorithms (2011, methodology): “Lock manipulation is performed entirely by the methods in the graph class; in addition, to enable rollback, each graph API method that modifies the graph makes a copy of the data before modification, as is done in other systems that use speculation such as transactional memory and thread-level specu”