Dune: Safe User-level Access to Privileged CPU Features
By A. Belay, Andrea Bittau, A. Mashtizadeh, David Terei, David Mazières, Christos Kozyrakis. USENIX Symposium on Operating Systems Design and Implementation, 2012
321 citations recorded by the source corpus.
View Paper: https://www.semanticscholar.org/paper/fa0ae1e61148b7a83d1fefde1708a02a18afc15a
How researchers see this paper
The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.
- Akshitha Sriraman
- Abhishek Dhanotia
- A. Belay
- R. Watson
- Simon Peter
- Christos Kozyrakis
- George Prekas
- Jonathan Woodruff
Citations in the corpus
- IX: A Protected Dataplane Operating System for High Throughput and Low Latency (2014, methodology): “Recent Linux Kernels support a busy polling driver mode that trades increased CPU utilization for reduced latency [27]”
- CHERI: A Hybrid Capability-System Architecture for Scalable Software Compartmentalization (2015, methodology): “Hypervisors have been used to provide contained execution environments [37], and Dune utilizes hardware virtualization features to accelerate intra-process isolation [6].”
- Arrakis (2014, result): “Our work was inspired in part by previous work on Dune [Belay et al. 2012], which used nested paging to provide support for user-level control over virtual memory, and Exitless IPIs [Gordon et al. 2012], which presented a technique to demultiplex hardware interrupts between virtual machines without…”
- The CHERI capability model: Revisiting RISC in an age of risk (2014, methodology): “To achieve coarse-grained software sandboxing of program components, efforts have been made to use process separation [36, 40], disjoint TLB sets in a shared process, static analysis of specially compiled binaries [24, 39, 48], and delegation of hypervisor support to userspace [3].”
- SoftSKU: Optimizing Server Architectures for Microservice Diversity @Scale (2019, background): “Software/hardware optimizations [54–62] that reduce context switch latency or counts might considerably improve Cache performance.”
- Accelerometer: Understanding Acceleration Opportunities for Data Center Overheads at Hyperscale (2020, background): “Software/hardware optimizations [28, 29, 32, 41, 44, 60, 73, 75, 116] that reduce scheduler latency (e.”