The CHERI capability model: Revisiting RISC in an age of risk
By Jonathan Woodruff, R. Watson, D. Chisnall, Simon W. Moore, Jonathan Anderson, Brooks Davis, B. Laurie, P. Neumann, Robert M. Norton, M. Roe. International Symposium on Computer Architecture, 2014
401 citations recorded by the source corpus.
Subfields: Artificial Intelligence, Computer Networks and Communications, Signal Processing
View Paper: https://www.semanticscholar.org/paper/0657eb7e069c2c2c7cae6636704e0f7fb3bcd9fc
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In Artificial Intelligence
In Computer Networks and Communications
Citations in the corpus
- SGXBOUNDS: Memory Safety for Shielded Execution (2017, methodology): “A number of memory-safety approaches have been implemented either in software [17, 38, 58, 59, 69] or in hardware [9, 10, 47, 81].”
- CHERI: A Hybrid Capability-System Architecture for Scalable Software Compartmentalization (2015, methodology): “In prior work, we have explored the baseline costs of CHERI memory protection [57].”